Paper Citation Record · LEDGER

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification

As of 20 August 2026, this Paper Citation Record lists 17 of 17 outbound references and 3 inbound Pith citation observations for arXiv:2505.06821.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2505.06821 v1

Coverage vector

measured 17 of 17 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-15T22:34:16.983623Z

measured 20 of 20 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-19T06:32:44.657259+00:00

measured 3 of 3 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-06T18:54:05.579429Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-15T18:26:27.109049Z

Reference resolution

17 of 17 outbound references displayed

verified exact0
verified fuzzy9
unresolved8
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation d0e572b8-8b74-4ec7-8190-0f4b3a06fe58 · outbound

This paper cites Tehranipoor, H.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification Tehranipoor, H

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:34:17.216355Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 7bbf495e-d3af-4d4b-8836-979ee4349229 · outbound

This paper cites Hardware trojan attacks: Threat analysis and countermeasures paper is a survey of the state-of-the-art trojan attacks, modeling,,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification Hardware trojan attacks: Threat analysis and countermeasures paper is a survey of the state-of-the-art trojan attacks, modeling,,

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:34:17.201671Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 52c5dc08-ad93-4893-b42a-831e991f8a0a · outbound

This paper cites Bench- marking of soc-level hardware vulnerabilities: A complete walkthrough,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification Bench- marking of soc-level hardware vulnerabilities: A complete walkthrough,

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-15T22:34:16.918789Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 76346c54-5519-4aa8-997e-2d62f25dd444 · outbound

This paper cites Llm for soc security: A paradigm shift,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification Llm for soc security: A paradigm shift,

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-15T22:34:16.924618Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 97a48eca-5dfc-44e3-8c87-a7322206a8c3 · outbound

This paper cites Empowering hardware security with llm: The development of a vulnerable hardware database,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification Empowering hardware security with llm: The development of a vulnerable hardware database,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:34:17.168041Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation c3d1304b-3fb8-41ef-a73a-81d62a449d09 · outbound

This paper cites Assert-o: Context- based assertion optimization using llms,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification Assert-o: Context- based assertion optimization using llms,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:34:17.152901Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 42e13bbd-ac82-4052-8863-f6d8025bf063 · outbound

This paper cites Nspg: Natural language processing-based secu- rity property generator for hardware security assurance,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification Nspg: Natural language processing-based secu- rity property generator for hardware security assurance,

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-15T22:34:16.939727Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9b5f0c2e-4321-428a-9d4c-c543337f9bf6 · outbound

This paper cites (security) assertions by large language models,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification (security) assertions by large language models,

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-15T22:34:16.944564Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 543df621-6696-4aaa-8047-57525a335083 · outbound

This paper cites [Online].

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification [Online]

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:34:17.119796Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation e949ed2c-f976-4f9b-aa1f-a48f1ab77eda · outbound

This paper cites SoCureLLM: An LLM-driven approach for large-scale system- on-chip security verification and policy generation,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification SoCureLLM: An LLM-driven approach for large-scale system- on-chip security verification and policy generation,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:34:17.104327Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation cfecd3ec-fb66-46b4-a1aa-8f39d28fde1f · outbound

This paper cites Exploring automated assertion generation via large language models,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification Exploring automated assertion generation via large language models,

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-15T22:34:16.957246Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9317a840-03ed-4adb-8bba-f09daa673b52 · outbound

This paper cites (2024) The neorv32 soc.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification (2024) The neorv32 soc

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:34:17.089298Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 32bcff68-e1f7-4804-901b-2f0f29baf65f · outbound

This paper cites The faiss library,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification The faiss library,

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-15T22:34:16.966438Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ae2c2587-36b6-4c04-8fc8-21fe533df761 · outbound

This paper cites Conference report from the 57th design automation conference,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification Conference report from the 57th design automation conference,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:34:17.065471Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 7c40a0e4-e847-4461-8fd6-2d922bc721b0 · outbound

This paper cites Sharpen: Soc security verification by hardware penetration test,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification Sharpen: Soc security verification by hardware penetration test,

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-15T22:34:16.975491Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e67f627d-bb0d-4a8c-a772-9f87acc89d36 · outbound

This paper cites Mab- fuzz: Multi-armed bandit algorithms for fuzzing processors,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification Mab- fuzz: Multi-armed bandit algorithms for fuzzing processors,

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-15T22:34:16.979564Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 745ece5b-e0e5-4ef9-935b-87280b8010a7 · outbound

This paper cites Psofuzz: Fuzzing processors with particle swarm optimization,.

ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification Psofuzz: Fuzzing processors with particle swarm optimization,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:34:17.031125Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Pith citing papers

Observation ae80009f-77bb-4a72-aac3-743dd156a81a · inbound

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation cites this paper.

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification

Reference 35

Resolution: unresolved; no resolver link, observed 2026-08-06T18:54:05.579429Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 22748f23-c89c-4c16-93ae-7d383587576e · inbound

Distilled Large Language Model in Confidential Computing Environment for System-on-Chip Design cites this paper.

Distilled Large Language Model in Confidential Computing Environment for System-on-Chip Design ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-06T15:18:32.308082Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation cd912065-1e07-4cf3-8583-7714b46392c1 · inbound

ATLAS: AI-Assisted Threat-to-Assertion Learning for System-on-Chip Security Verification cites this paper.

ATLAS: AI-Assisted Threat-to-Assertion Learning for System-on-Chip Security Verification ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification

Reference 46

Resolution: verified exact; arxiv_id, observed 2026-05-15T18:26:27.112176Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.