Thermal Capacity Mapping of Cryogenic Platforms for Quantum Computers

Large-scale cryogenic Input-Output (IO) infrastructure is a requirement for realising fault-tolerant quantum computing in solid-state modalities. Such IO scaling presents significant challenges in thermal modelling, hardware design and verification. Here we present a design tool for cryogenic platform development with applicability to quantum computing and other cryogenic technologies. By taking comprehensive measurements of a commercially available dilution refrigerator we construct a 'platform capacity map', quantifying the platform's complex response to heat loads distributed over multiple temperature stages and accounting for interstage dependencies, avoiding an analytical model. This allows for the modification of the platform parameters to be accurately estimated for the inclusion of an arbitrary IO infrastructure, the identification of stage thermal overheads and the optimisation of system parameters. We identify a key bottleneck around the Still stage, owing to loading from connected stages, and observe discrepancies between existing thermal modelling methods for estimating heat loads associated with IO and experimental results obtained from the platform capacity map.