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REVIEW 4 major objections 6 minor 38 references

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

T0 review · 4 major / 6 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read A 6T SRAM cell built from minimum-size transistors can match conventional read stability when the word-line voltage is trimmed during reads.

desk verdict Real silicon stability data for a minimum-size 6T cell, but the headline SER benefit is model extrapolation, not measurement. read the letter →

arxiv 2411.18114 v1 pith:RRDZ7NOL submitted 2024-11-27 cs.AR

Gabriel Torrens (1) , Bartomeu Alorda (1) , Cristian Carmona (1) , Daniel Malagon-Perianez (1) , Jaume Segura (1) , Sebastia Antoni Bota (1) ((1) University of the Balearic Islands) This is my paper · ORCID
classification cs.AR
keywords 6TSRAMminimum-sizetransistorscellratioreadstaticnoisemarginword-linevoltagemodulationsofterrorrateleakagepower65nmCMOS
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that the conventional requirement of a 6T SRAM cell ratio between 1.5 and 2.5 is not necessary: a cell with all six transistors at minimum size, cell ratio 1 and pull-up ratio 1, can be a reliable, higher-density building block. The main penalty of this choice is read stability, which falls by about 25% in RSNM, but the paper shows that lowering the word-line voltage by 10% during read restores RSNM to the level of a conventional CR=2 cell. If the claim holds, the minimum-size cell yields about 25% area reduction, over 35% lower leakage, lower write energy, and about 30% lower per-bit soft-error rate, all in a 65-nm CMOS technology. The paper backs the stability and writeability conclusions with measurements on a fabricated 16-kb array.

What carries the argument

Two named objects carry the argument. The first is the minimum-size 6T cell (6T-MSC), defined by cell ratio $CR=W_n/W_{acc}=1$ and pull-up ratio $PR=W_p/W_{acc}=1$, compared against a conventional CR=2 cell (6T-CC); the second is the word-line voltage modulation read assist, which restores the lost read stability. Stability is measured through RSNM in simulation and through SRRV on silicon, with an equivalence relation between the two metrics used to convert measured SRRV into read-failure probability. The soft-error analysis runs through Eq. (1), which weights nMOS and pMOS sensitive drain areas and critical charges, together with linear fits of $Q_{crit}$ to transistor widths (Eqs. 2-3); the parameters in Table I come from fitted alpha-irradiation experiments on the same 65-nm technology.

What would settle it

Build matched 16-kb arrays of 6T-MSC and 6T-CC cells in the same 65-nm process, expose them to a calibrated alpha source at 1.2 V, and compare per-bit upset counts; a measured ratio near 1.0 rather than about 0.7 would refute the soft-error claim. Measuring RSNM of 6T-MSC at WL=1.0 V against 6T-CC at 1.2 V would directly test the read-assist recovery.

Watch

Extended reading notes

Core claim

On the paper's own terms, the discovery is that the read-stability barrier to minimum-size 6T cells is removable without changing the cell. The authors show via simulation that writeability is essentially independent of CR, that RSNM drops about 25% when CR goes from 2 to 1, and that a 10% word-line voltage reduction during read brings RSNM back to the conventional value. They also evaluate power and radiation: minimum-size cells reduce leakage by more than 35%, lower write energy, and, through smaller drain areas that dominate charge collection, lower the alpha-induced per-bit soft-error rate by about 30% even though critical charge is lower. Experimental SRRV distributions from a 16-kb 65-nm array confirm adequate write margins and confirm that the word-line assist recovers read stability under process variability.

Load-bearing premise

The most load-bearing assumption is that the fitted alpha-particle soft-error model and the SRRV-RSNM equivalence are accurate for the minimum-size cell, and that a 10% word-line drop does not damage writeability or half-selected cells.

Editorial extensions

If this is right

  • Cell area decreases by roughly 25% versus a CR=2 cell with PR=1, directly reducing memory cost per bit.
  • Leakage current falls by more than 35% and write energy drops because all internal capacitances shrink.
  • Read stability is the main casualty: RSNM falls by about 25%, but lowering word-line voltage by 10% during read restores RSNM to the conventional-cell value at nominal voltage.
  • Measured SRRV on a fabricated 16-kb 65-nm array confirms writeability is safe and confirms the SRRV recovery when WL is reduced from 1.2 V to 1.0 V.
  • The modelled per-bit soft-error rate improves by about 30% despite a 30% lower critical charge, because the smaller drain areas reduce charge collection cross-section.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Inference: In technologies where transistor widths are quantized (e.g., FinFET fin counts), the CR=1 design point is the natural density extremum, so the same area-leakage-SER trade-off would reappear with a one-fin pull-down; the paper's WL-modulation result suggests the read-assist burden is portable.
  • Inference: The SER improvement is a model prediction, not a measured endpoint; a direct alpha or neutron irradiation campaign comparing matched 6T-MSC and 6T-CC arrays would either confirm the ~30% per-bit advantage or expose where the fitted cross-section model overestimates.
  • Inference: Because WL modulation is active only during access, the simulated read-delay increase (about 190 ps to 272 ps at the cell level) may be absorbed by pipeline timing; whether the density gain survives at macro level depends on the memory's timing budget, which the paper does not fully close.
  • Inference: WL modulation during write also helps half-selected cells, as the paper notes; a full-array study of write margins and dynamic power with the assist enabled, including the 1.19e-4 failure probability at Vcell 10% below nominal, would quantify the system-level reliability envelope.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper proposes a 6T SRAM bit-cell with all minimum-size transistors (cell ratio CR=1 and pull-up ratio PR=1), called the 6T-MSC, as an alternative to conventional cells with CR between 1.5 and 2.5 (6T-CC). Using electrical simulation and a fabricated 16-kb 65-nm test array, the authors analyze the impact of CR=1 on area, leakage, write energy, read/write timing, read stability, writeability, and soft-error rate. They report about 25% area reduction, more than 35% leakage reduction, lower write energy, improved writeability, a 25% RSNM degradation that can be recovered by a 10% word-line voltage reduction, and about 30% soft-error rate improvement per bit. The experimental part provides WLVM and SRRV distributions and March-test functionality for the 6T-MSC array, but contains no direct measurement of SER, leakage, or area, and no comparison against a 6T-CC control array on the same silicon.

Significance. If the central claims hold, the paper provides a useful design point for high-density SRAM: a regular, minimum-size 6T layout with DFM-friendliness and achievable stability via word-line read assist. The experimental stability data (WLVM, SRRV distributions, March tests) are concrete and support the writeability and read-stability statements for the 6T-MSC itself. The paper is also honest about read-speed degradation, and the analysis covers several metrics (area, leakage, write energy, timing, SER) in a single coherent framework. However, the headline SER improvement is a model extrapolation, not a measurement, and several quantitative claims (area, leakage, write energy) are not validated by the fabricated test chip. These gaps undermine the strength of the abstract's quantitative promises, even though the qualitative direction of the results is plausible.

major comments (4)
  1. [III.C] The claimed soft-error-rate improvement of around 30% (Abstract and Section VII) is not measured in this work. It is the output of Eq. (1) with parameters in Table I and with Qcrit-width linear relations given in Eqs. (2)-(3), which are not actually printed in the manuscript text. The Table I parameters are attributed to reference [33], but [33] is Hazucha and Svensson's neutron-SER paper, not an alpha-irradiation fitting source; the companion reference [24] by the same group is the apparent alpha-fitting source. Since Eq. (1) balances a linear increase of sensitive drain area against an exponential increase of Qcrit with width, the sign and magnitude of the SER-versus-CR trend in Fig. 9 are entirely controlled by fitted constants that were not re-validated on the 6T-MSC or on the 65-nm test chip. The authors should either provide direct alpha/neutron SER measurements of both 6T-MSC and 6T-CC cells, or present a sensitivity analysis showing the claimed 30% benefit is robust to the fitted constant uncertainties, or soften the abstract claim to a simulation-based estimate.
  2. [VI] The fabricated 16-kb SRAM contains only 6T-MSC cells; there is no on-chip 6T-CC control array. Consequently, the experimentally supported part of the paper is limited to '6T-MSC alone is functional and has acceptable WLVM/SRRV with word-line assist.' The claims that a 10% word-line reduction yields the same RSNM as a 6T-CC (Section III.B, Fig. 8) and that the 6T-MSC is comparable to a conventional cell remain simulation-only. Moreover, the SRRV failure-probability extrapolations assume Gaussian tails and rely on an SRRV/RSNM equivalence from [27], which was demonstrated in 28-nm FDSOI, not 65-nm bulk CMOS. The authors should either compare measured 6T-CC and 6T-MSC SRRV/RSNM distributions, or clearly restrict the experimental conclusions to the 6T-MSC itself.
  3. [IV] The reported leakage reduction of more than 35% and the write-energy improvement are simulation results only; Section IV uses Eq. (4) with no measured power or leakage data from the fabricated chip. Since the Abstract presents these improvements as quantitative findings, the paper should either provide measured IDDQ/energy data or explicitly state in the Abstract and conclusions that these are simulation predictions. A calibration of the leakage model against the fabricated 65-nm process would substantially strengthen the claim.
  4. [II.B] The 25% area reduction claim relative to a CR=2 cell is based on the layout sketches in Fig. 2 and the curve in Fig. 3, but no DRC-clean dimensions, contacted-poly pitch, metal pitch, or memory-cell height/width numbers are reported. Since area is one of the paper's central advertised benefits, the authors should provide the actual cell dimensions or a design-rule-based area calculation (including well, implant, and contact enclosure rules) to substantiate the 25% figure and to clarify whether the comparison assumes equal bit-line pitch and word-line pitch.
minor comments (6)
  1. [III.C] Equations (2) and (3), which are essential for the SER computation in Fig. 9, are missing from the published text; only the numbered placeholders appear. The authors should include the explicit linear Qcrit-width relations.
  2. [I/References] The reference list cites [33] as Hazucha and Svensson's atmospheric neutron SER paper, but Table I and the text describe alpha-particle fitting from 65-nm SRAM experiments. Please correct the citation to the actual alpha-irradiation source (likely [24] or a companion paper).
  3. [III.B/IV] In the sentence defining thermal voltage, 'V_th=qT/k' should be 'kT/q'; the symbol q is used elsewhere for charge, which is confusing.
  4. [Fig. 10] The caption 'Power consumption and IDDQ' is unclear; the figure appears to show both leakage current and write energy, not just IDDQ. Please clarify the vertical axes and units.
  5. [VI] The March-test description does not specify the test algorithm (e.g., March C-, March SS), the background pattern, or the number of test repetitions. Adding these details would improve reproducibility.
  6. [II.B] The claim that the 6T-MSC layout has 'absence of bends in the n-diffusion' (Section II.B) is only valid for the specific layout style shown in Fig. 2(a); other standard-cell layout styles may also use straight diffusion. Please phrase this as a property of the chosen layout rather than of the minimum-size cell in general.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the read-stability result is experimentally verified on a fabricated 16-kb 6T-MSC array, and the SER benefit is a model extrapolation from previously calibrated alpha-SER parameters, not a derivation from the claim itself.

full rationale

The paper's central stability claim does not reduce to its inputs. RSNM degradation at CR=1 and its recovery by word-line voltage modulation are obtained from electrical simulation and then corroborated on a fabricated 16-kb 6T-MSC array by measuring WLVM and SRRV (Figs. 12-13), using the SRRV/RSNM equivalence of [27] as an external calibration. Area, leakage, and write-energy comparisons are direct layout/device-width consequences (CR=Wn/Wacc by definition, Eq. (4) for subthreshold leakage), not hidden fits. The only model-based result is the approximately 30% soft-error-rate-per-bit improvement (Abstract; Section III.C). That figure is computed from Eq. (1) with Table I parameters 'obtained from fitting of experimental results performed with alpha irradiation of a 65 nm SRAM,' together with linear Qcrit-versus-width relations from electrical simulation. This is a calibrated empirical model applied to a new cell sizing, not a circular derivation: the parameter values were fixed by prior irradiation data, and the paper does not fit them to the 6T-MSC/6T-CC comparison it reports. The absence of a dedicated SER measurement in this paper and the confusing attribution of Table I to [33] (a neutron-SER work) are correctness and reproducibility caveats, but they do not make the claim equivalent to its inputs by construction. No self-citation is used to forbid alternatives or to supply an unverified uniqueness result.

Assumptions & free parameters 3 free parameters · 6 assumptions · 0 invented entities

The central claims rest on assumptions about leakage physics, the equivalence of SRRV and RSNM, Gaussian variability, and an alpha-SER model whose constants are fitted. The SER advantage is a model output; stability is measured. No new physical entities are introduced. Three free parameter groups are used: the hand-chosen WL assist voltage and the fitted SER model constants.

free parameters (3)
  • Word-line assist voltage during read (VWL) = 1.0 V (about 10% below nominal 1.2 V)
    Chosen by hand in Sections III.B and VI to make 6T-MSC RSNM/SRRV match the conventional cell; it is a tunable design setting, not derived from first principles.
  • SER exponential model constants beta_e and beta_h = 4.95e14 C^-1 (electrons), 1.26e15 C^-1 (holes)
    Table I reports parameters obtained from fitting alpha-irradiation experiments on 65-nm SRAM. These constants set the exponential sensitivity in Eq. (1) and directly shape the SER-versus-CR result in Fig. 9.
  • Qcrit width-scaling coefficients a, b, c (electrons and holes) = electrons: a=0.45 fC, b=3.6 fC/um, c=6.5 fC/um; holes: a=0.53 fC, b=11.3 fC/um, c=2.67 fC/um
    Eqs. (2)-(3) and Table I; obtained from fitting electrical simulation and experimental data. They convert transistor widths into critical charge, and therefore into SER.
assumptions (6)
  • domain assumption Subthreshold leakage follows the BSIM-style equation (4) with constant parameters; leakage is dominated by ISUB through off-state transistors.
    Section IV uses Eq. (4) and identifies IS1, IS2, IS3 as the main leakage components; no measurement of leakage is reported.
  • domain assumption SRRV and RSNM cumulative density functions give equivalent read failure probability estimates [27].
    Section III.B uses SRRV as a proxy for read stability to validate simulation results experimentally; the equivalence is imported from the cited literature.
  • domain assumption Read disturb voltage VREAD and inverter trip point VTRIP are the relevant failure mechanism; VTRIP is approximated by the inverter switching voltage [25].
    Section III.B bases the RSNM analysis on the VREAD versus VTRIP comparison.
  • domain assumption Process variability is Gaussian; large local Vt variability is the dominant source of margin degradation and is captured by Monte Carlo with reported sigmas.
    Section VI assumes Gaussian distributions to extrapolate SRRV tails to failure probabilities of 1e-9 and 1e-21.
  • domain assumption The alpha-SER model of Eq. (1) [35] and the linear Qcrit-width relations of Eqs. (2)-(3) [33] are valid for the 65-nm technology in question.
    The SER comparison in Section III.C depends on these imported models; the constants are fitted, not independently verified in this paper.
  • domain assumption Straight-diffusion layout removes a source of misalignment-induced variability [21], partially compensating the Vt variation increase from dopant fluctuation [22].
    Section II.B argues a DFM benefit of the minimum-size layout; this is qualitative and not directly measured in this paper.

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Cite this review

Pith. "Pith review of A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors." pith.science (2026). https://pith.science/paper/RRDZ7NOL

@misc{pith2026241118114,
  author       = {Pith},
  title        = {Pith review of: A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/RRDZ7NOL}},
  note         = {Machine review of arXiv:2411.18114}
}
read the original abstract

As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised between 1.5-2.5 to 1. The impact of this option on area, power, performance and stability is analyzed showing that the most affected parameter is read stability, although this impact can be overcome using some of the read assist circuits proposed in the literature. The main benefits are layout regularity enhancement, with its consequent higher tolerance to variability, cell area reduction by 25% (with respect to a cell having a cell ratio of 2), leakage current improvement by a 35%, as well as energy dissipation reduction and a soft error rate per bit improvement of around 30%.

Figures

Figures reproduced from arXiv: 2411.18114 by the authors.

Figure 2
Figure 2. (a) Layout of 6T-cell with minimum size transistors (b) 6T-cell with [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 4
Figure 4. Graphical definition of WNM [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 13
Figure 13. Experimental distribution of SRRV in the 6T-MSC cell SRAM. [PITH_FULL_IMAGE:figures/full_fig_p007_13.png] view at source ↗

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Reference graph

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Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.