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REVIEW 3 major objections 6 minor 58 references

Multi-Strided Access Patterns to Boost Hardware Prefetching

T0 review · 3 major / 6 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read Restructuring a single memory stride into several concurrent strides can speed up memory-bound kernels by giving the hardware prefetcher more streams to track.

desk verdict Well-measured demonstration that multi-strided access primes Intel's hardware prefetcher; the core mechanism is proven only on Coffee Lake, but the microbenchmark design is solid and the paper deserves a serious referee. read the letter →

arxiv 2412.16001 v1 pith:SP2GZGXW submitted 2024-12-20 cs.PF

Miguel O. Blom , Kristian F. D. Rietveld , Rob V. van Nieuwpoort This is my paper · ORCID
classification cs.PF
keywords hardwareprefetchingmulti-stridingmemory-boundkernelsaccesspatternsloopunrollingcachehitratioAVX2collisions
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that a memory-bound loop can be made faster by restructuring its single sequential access stream into several streams that are touched concurrently, because the CPU's hardware prefetcher then tracks multiple streams at once. The authors show on micro-benchmarks that load bandwidth rises by up to 33% without software prefetch instructions, and that the effect disappears when the hardware prefetcher is disabled. They then apply the transformation to six dense kernels on three x86-64 microarchitectures and report speedups over established library and compiler baselines. If the claim holds, multi-striding is a compiler-applicable optimization for a broad class of memory-bound kernels.

What carries the argument

The central object is stride unrolling: unrolling a loop over any axis other than the contiguous data axis so the loop body touches several sequential address streams at once, while portion unrolling (unrolling along the contiguous axis) remains the single-stride comparison. The transformation first identifies the critical memory access, applies loop interchange so the innermost loop follows the contiguous axis, vectorizes along it, and then instantiates AVX2 assembly templates that keep the total number of loop-body unrolls fixed and vary only the number of strides. The hardware prefetcher is the device being exploited: with several strides in flight it can predict at several positions concurrently, which raises L2/L3 hit ratios even in kernels with no data reuse.

What would settle it

Run the same multi-strided kernel sweep on one of the two microarchitectures for which the paper does not include a prefetcher-off test, with the hardware prefetcher disabled; if multi-strided configurations still beat single-strided ones by the same margin, the paper's prefetcher-priming explanation is wrong.

Watch

Extended reading notes

Core claim

The central claim is that converting one sequential access stream into several concurrent sequential streams, a transformation the paper calls multi-striding, lets the hardware prefetcher make predictions at multiple positions at once, so more cache lines arrive before they are needed. With the prefetcher disabled, the measured gains disappear, confirming the mechanism on the machine where that test was run. In micro-benchmarks on one Intel microarchitecture, load throughput rises by up to 33% at sixteen strides, and the best multi-strided variants of six dense kernels beat established baselines on three x86-64 microarchitectures, including up to 2.99x over a vendor-tuned dense linear algebra library and up to 2.18x over the paper's own single-strided assembly baseline.

Load-bearing premise

The load-bearing premise is that the speedups are caused by the hardware prefetcher following the extra memory streams, a cause verified by a prefetcher-off test on only one of the three machines tested.

Editorial extensions

If this is right

  • Compilers can implement multi-striding with existing loop transformations, unrolling over the non-contiguous axis and using interchange or blocking to expose the contiguous axis, so the method is a candidate for automatic optimization.
  • Memory-bound dense kernels can outperform both compiler-vectorized code and hand-tuned library implementations without inserting software prefetch instructions.
  • The speedup comes with a data-layout constraint: simultaneous strides must map to different cache sets, so power-of-two-sized buffers need padding or blocking to avoid conflict misses.
  • The benefit applies to cached loads and regular writes, but not to non-temporal streaming writes, which bypass the cache and are limited by the write buffer.
  • The pattern produced bandwidth and kernel gains on three x86-64 microarchitectures, though the best number of strides varies by kernel and microarchitecture.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial extension: the number of strides a loop uses could be tuned per architecture to match how many independent streams the prefetcher can track, in the same way compilers already tune unroll factors.
  • Editorial extension: the paper studies single-core execution, so in multithreaded runs multiple cores issuing multi-strided streams may contend for shared L3 and main-memory bandwidth, possibly shrinking the gains.
  • Editorial extension: the cache-collision result gives a practical recipe for power-of-two-sized buffers: pad or block the data so simultaneous strides fall into different cache sets before applying multi-striding.
  • Editorial extension: the non-temporal store results suggest a hybrid variant, not explored by the paper, that applies multi-striding only to the load side of a copy or streaming kernel while keeping writes grouped.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper introduces 'multi-striding', a transformation that replaces a single-strided memory traversal by concurrent access to multiple strides, obtained by unrolling a loop along a non-contiguous axis so that several hardware prefetcher streams are primed at once. On an Intel Coffee Lake system, AVX2 micro-benchmarks show that read throughput increases with the number of strides (up to 33% at 16 strides), that L2/L3 hit ratios improve, and that the gains disappear when the hardware prefetcher is disabled. The transformation is applied to six dense compute kernels, and the best generated configurations are compared with single-strided assembly, Clang/Polly, MKL, OpenBLAS, Halide, and OpenCV on Coffee Lake, Cascade Lake, and Zen 2, with speedups up to 2.99x over MKL. The authors argue that multi-striding is a natural extension of loop unrolling and loop interchange and is suitable for compiler pipelines.

Significance. The micro-benchmark analysis in Sections 4.2-4.6 is careful and well controlled on Coffee Lake: the loop body is kept at a constant 32 unrolls, CPU frequency is locked, prefetching is toggled via MSR, and stall and hit-ratio counters from perf support the prefetcher-priming story. The paper also gives a falsifiable prediction - the multi-stride benefit should vanish when prefetching is disabled - and verifies it for reads and stores on that platform. If the causal mechanism were confirmed on the other two microarchitectures, multi-striding would be a genuinely useful compiler-oriented transformation for memory-bound dense kernels. The significance is currently moderated by the single-platform causal control and by the best-of-N configuration selection used for the kernel speedups.

major comments (3)
  1. [Section 4.3 / Section 6.3] The prefetcher-off control that establishes the causal mechanism is only reported for the Coffee Lake microarchitecture of Section 4.2. The bicg kernel plot in Section 6.3 is labeled only as 'with and without hardware prefetching' and is not tied to a microarchitecture, and no prefetcher-off or hit-ratio measurements are given for Cascade Lake or Zen 2 in Sections 6.3-6.4. Since the abstract and conclusion generalize the prefetcher-utilization mechanism to three microarchitectures, the stated causal explanation is not supported outside Coffee Lake; memory-level parallelism, cache-set behavior, or instruction scheduling remain plausible alternative explanations for the kernel speedups on the other two systems.
  2. [Section 6.4] The state-of-the-art comparison reports the 'highest recorded throughput among the used sizes of the data' for each kernel and microarchitecture, after searching configurations with up to 50 total unrolls distributed over stride unroll and portion unroll. No variance, confidence intervals, or significance tests are reported for these selected maxima, and each kernel's best configuration is chosen post hoc. This best-of-N reporting makes the magnitude of the headline speedups (e.g., 2.99x over MKL, 12.55x over Polly) hard to interpret and risks overfitting to the specific machines and array sizes; the authors should report the distribution across configurations and either pre-register the configuration-selection rule or validate it with a hold-out set.
  3. [Section 6.2] The Coffee Lake experiments in Section 4.2 lock the CPU frequency to 3.2 GHz, disable Turbo Boost and deep C-states, and enable huge pages, but the multi-architecture setup in Section 6.2 does not state equivalent frequency or power-management controls for Cascade Lake and Zen 2. If frequency scaling remained active on those machines, run-to-run frequency variation could account for part of the reported speedups; the authors should document the same controls for all platforms or demonstrate that the results are insensitive to them.
minor comments (6)
  1. [Abstract / Section 7] The abstract states a speedup of 12.55x over Polly while the conclusion states 12.25x over CLang combined with Polly; please reconcile these numbers and clarify which baseline is meant.
  2. [Section 5.1.1] The 'critical memory access' is defined informally in prose and the selection rule is not validated against the kernels' actual memory-bound behavior; consider formalizing the definition and checking whether it selects the bottleneck access in each surveyed kernel.
  3. [Section 5.1.2] The register-pressure feasibility check is described only verbally; please provide the exact register limit, the spilling criterion, and the elimination rules for redundant loads and stores.
  4. [Section 1] The paper repeatedly claims the kernels are produced 'without low-level hand optimization', yet the assembly is generated by purpose-written Python scripts and the critical access and best configuration are chosen manually; please qualify this claim so readers can judge the level of automation.
  5. [Section 6.4] The statement that CLang outperforms multi-striding for jacobi2d because of shuffle and permutation instructions would benefit from a reference to the generated code or a disassembly excerpt.
  6. [Section 1] The introduction promises an open-source artifact before publication; since the paper is under submission, an artifact URL or appendix with the generation scripts would strengthen reproducibility.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the claimed prefetcher benefit is established by controlled micro-benchmarks and external baselines, not by definition or self-citation.

full rationale

The paper's central claim is empirical: multi-strided access patterns improve hardware-prefetcher utilization and kernel throughput. The micro-benchmark design isolates the striding effect by construction rather than equivocating it with the result: 'the only differences between configurations of the micro-benchmark are: (1.) the offsets at which each instruction accesses data and (2.) the step-size by which we increment the base register.' The mechanism is then tested directly with the prefetcher disabled: 'we test with the hardware prefetcher disabled. And indeed, as can be seen in the bottom left graph of Figure 2, no improvement occurs in this case.' Since the prefetcher-off control removes the proposed causal mechanism and the improvement disappears, the causal claim is externally falsifiable, not definitional. Kernel results are compared against independent references (MLC, STREAM, MKL, OpenBLAS, Halide, OpenCV, Polly), so the headline speedups are not fitted values renamed as predictions. The choice of the best configuration from a generated search space is tuning, not a circular prediction. There are no self-citations of the authors, no imported uniqueness theorem, and no ansatz smuggled in via citation. The main weakness—the prefetcher-off control is only reported for Coffee Lake, so the mechanism is not directly verified on Cascade Lake and Zen 2—is a generalizability/evidence gap, not circularity: nothing in the paper defines the multi-stride speedup in terms of itself. Overall this is a self-contained empirical study with no significant circularity.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

No mathematical derivation is claimed. The speedup claims rest on empirically tuned configuration choices and on hardware prefetching behavior, which is the main unverified-to-other-architectures assumption.

free parameters (2)
  • stride_unroll_and_portion_unroll_per_kernel = kernel- and machine-specific, e.g., best stride counts mostly in 1 to 10; chosen from 1 to 50 total unrolls
    The optimal multi-striding configuration is selected empirically per kernel and per microarchitecture from a large generated space; the paper does not predict these values ahead of time.
  • data_array_size_in_gib = 2 to 4 GiB, plus 1.9 GiB for the microbenchmark collision probe
    Array sizes are chosen to exceed the L3 cache and satisfy divisibility and alignment constraints; the 2.0 GiB exact power-of-two case is used to demonstrate cache collisions.
assumptions (4)
  • domain assumption Hardware prefetchers can be primed to track multiple concurrent strides and fetch data into L2/L3 ahead of access.
    This is the core mechanism; it is verified on Coffee Lake via prefetcher-disabled controls, but assumed to transfer to Cascade Lake and Zen 2.
  • domain assumption Kernels are dense, row-major, and free of loop-carried dependencies, so loop interchange and vectorization are semantics-preserving.
    Section 5.1 states these as requirements; this restricts the scope to regular memory-bound dense kernels.
  • ad hoc to paper The critical memory access is the highest-dimensional array whose last indexing variable appears only in the last position of every array reference.
    Section 5.1.1 introduces this heuristic without proof; it could misidentify the bandwidth bottleneck for kernels with multiple large arrays.
  • domain assumption AVX2 non-temporal stores are no-write-allocate on the tested microarchitectures, per Intel documentation.
    Section 4.4 uses this behavior to explain why non-temporal stores do not benefit from multi-striding.

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Cite this review

Pith. "Pith review of Multi-Strided Access Patterns to Boost Hardware Prefetching." pith.science (2026). https://pith.science/paper/SP2GZGXW

@misc{pith2026241216001,
  author       = {Pith},
  title        = {Pith review of: Multi-Strided Access Patterns to Boost Hardware Prefetching},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/SP2GZGXW}},
  note         = {Machine review of arXiv:2412.16001}
}
read the original abstract

Important memory-bound kernels, such as linear algebra, convolutions, and stencils, rely on SIMD instructions as well as optimizations targeting improved vectorized data traversal and data re-use to attain satisfactory performance. On on temporary CPU architectures, the hardware prefetcher is of key importance for efficient utilization of the memory hierarchy. In this paper, we demonstrate that transforming a memory access pattern consisting of a single stride to one that concurrently accesses multiple strides, can boost the utilization of the hardware prefetcher, and in turn improves the performance of memory-bound kernels significantly. Using a set of micro-benchmarks, we establish that accessing memory in a multi-strided manner enables more cache lines to be concurrently brought into the cache, resulting in improved cache hit ratios and higher effective memory bandwidth without the introduction of costly software prefetch instructions. Subsequently, we show that multi-strided variants of a collection of six memory-bound dense compute kernels outperform state-of-the-art counterparts on three different micro-architectures. More specifically, for kernels among which Matrix Vector Multiplication, Convolution Stencil and kernels from PolyBench, we achieve significant speedups of up to 12.55x over Polly, 2.99x over MKL, 1.98x over OpenBLAS, 1.08x over Halide and 1.87x over OpenCV. The code transformation to take advantage of multi-strided memory access is a natural extension of the loop unroll and loop interchange techniques, allowing this method to be incorporated into compiler pipelines in the future.

Figures

Figures reproduced from arXiv: 2412.16001 by the authors.

Figure 1
Figure 1. Illustration of the difference between a single [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Measured throughput of different memory operations for increasing numbers of strides on the Core i7-8700 platform. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Execution stalls with outstanding loads for L1 data, [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (4 more)
Figure 4
Figure 4. Figure 4: Cache hit ratio for different cache levels with and [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: Throughput in gigibytes per second using different [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: Throughput of different isolated parts of compute kernels for different striding configurations. [PITH_FULL_IMAGE:figures/full_fig_p009_6.png]
Figure 7
Figure 7. Figure 7: Speedup in throughput of the best multi-strided configuration of the six compute kernels compared to state-of-the-art [PITH_FULL_IMAGE:figures/full_fig_p010_7.png]

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Works this paper leans on

58 extracted references · 38 canonical work pages

  1. [1]

    Andrew Adams, Karima Ma, Luke Anderson, Riyadh Baghdadi, Tzu-Mao Li, Michaël Gharbi, Benoit Steiner, Steven Johnson, Kayvon Fatahalian, Frédo Du- rand, and Jonathan Ragan-Kelley. 2019. Learning to optimize halide with tree search and random programs. ACM Trans. Graph. 38, 4, Article 121 (July 2019), 12 pages. https://doi.org/10.1145/3306346.3322967

    arXiv 2019

  2. [3]

    Hossein Amiri and Asadollah Shahbahrami. 2017. High performance imple- mentation of 2D convolution using Intel’s advanced vector extensions. In 2017 Artificial Intelligence and Signal Processing Conference (AISP) . 25–30. https: //doi.org/10.1109/AISP.2017.8324097

    work page arXiv 2017

  3. [4]

    Jean-Loup Baer and Tien-Fu Chen. 1991. An effective on-chip preloading scheme to reduce data access penalty. In Proceedings of the 1991 ACM/IEEE Conference on Supercomputing (Albuquerque, New Mexico, USA) (Supercom- puting ’91). Association for Computing Machinery, New York, NY, USA, 176–186. https://doi.org/10.1145/125826.125932

    work page arXiv 1991

  4. [5]

    Bender, Rathish Das, Martín Farach-Colton, and Guido Tagliavini

    Michael A. Bender, Rathish Das, Martín Farach-Colton, and Guido Tagliavini

    work page

  5. [6]

    Gratz, and Daniel A

    Eshan Bhatia, Gino Chacon, Seth Pugsley, Elvira Teran, Paul V. Gratz, and Daniel A. Jiménez. 2019. Perceptron-Based Prefetch Filtering. In 2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA) . 1–13. https://doi.org/10.1145/3307650.3322207

    arXiv 2019

  6. [7]

    Meisam Booshehri, Abbas Malekpour, and Peter Luksch. 2013. An Improving Method for Loop Unrolling. International Journal of Computer Science and Infor- mation Security 11, 5 (2013), 73–76. https://doi.org/10.48550/ARXIV.1308.0698

    work page Pith review arXiv doi:10.48550/arxiv.1308.0698 2013

  7. [8]

    Chen and J.-L

    T.-F. Chen and J.-L. Baer. 1994. A performance study of software and hardware data prefetching schemes. SIGARCH Comput. Archit. News 22, 2 (April 1994), 223–232. https://doi.org/10.1145/192007.192030

    work page arXiv 1994

  8. [9]

    Intel Corporation. 2024. Intel Memory Latency Checker . https: //www.intel.com/content/www/us/en/developer/articles/tool/intelr-memory- latency-checker.html Version 3.11

    work page 2024

Show all 58 references
  1. [10]

    Davidson and Sanjay Jinturkar

    Jack W. Davidson and Sanjay Jinturkar. 1995. Improving instruction-level par- allelism by loop unrolling and dynamic memory disambiguation. In Proceed- ings of the 28th Annual International Symposium on Microarchitecture . 125–132. https://doi.org/10.1109/MICRO.1995.476820

    1995

  2. [11]

    Yingshuai Dong, Chencheng Ye, Haikun Liu, Liting Tang, Xiaofei Liao, Hai Jin, Cheng Chen, Yanjiang Li, and Yi Wang. 2024. DTAP: Accelerating Strongly-Typed Programs with Data Type-Aware Hardware Prefetching.ACM Trans. Archit. Code Optim. (Oct. 2024). https://doi.org/10.1145/37...

    2024 doi

  3. [12]

    Hikmet Dursun, Ken-ichi Nomura, Weiqiang Wang, Manaschai Kunaseth, Liu Peng, Richard Seymour, Rajiv K Kalia, Aiichiro Nakano, and Priya Vashishta

  4. [13]

    Babak Falsafi and Thomas F. Wenisch. 2014. A Primer on Hardware Prefetching . Springer International Publishing. https://doi.org/10.1007/978-3-031-01743-8

    2014 doi

  5. [14]

    Jason E. Fritts. 2000. Cache write policy for streaming output data. In 2nd Workshop on Media Processors and DSPs (held in conjunction with MICRO-33) . 13–22. https://api.semanticscholar.org/CorpusID:2894673

    2000

  6. [15]

    Adi Fuchs, Shie Mannor, Uri Weiser, and Yoav Etsion. 2014. Loop-Aware Memory Prefetching Using Code Block Working Sets. In Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (Cambridge, United Kingdom) (MICRO-47). IEEE Computer Society, USA, 5...

    2014 doi

  7. [16]

    Shaleen Garg, Jian Zhang, Rekha Pitchumani, Manish Parashar, Bing Xie, and Sudarsun Kannan. 2024. CrossPrefetch: Accelerating I/O Prefetching for Modern Storage. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Oper...

    2024

  8. [17]

    Diana Guttman, Meenakshi Arunachalam, Vlad Calina, and Mahmut Taylan Kandemir. 2015. Prefetch Tuning Optimizations. Vol. 2. Elsevier Inc., United States, 401–419. https://doi.org/10.1016/B978-0-12-803819-2.00018-5

    2015 doi

  9. [18]

    Hemeida, S.A

    A.M. Hemeida, S.A. Hassan, Salem Alkhalaf, M.M.M. Mahmoud, M.A. Saber, Ayman M. Bahaa Eldin, Tomonobu Senjyu, and Abdullah H. Alayed. 2020. Op- timizing matrix-matrix multiplication on Intel’s advanced vector extensions multicore processor. Ain Shams Engineering Journal 11, 4 ...

    2020 doi

  10. [19]

    Brown, and Zhenlin Wang

    Jason Hiebel, Laura E. Brown, and Zhenlin Wang. 2019. Machine Learning for Fine-Grained Hardware Prefetcher Control. In Proceedings of the 48th In- ternational Conference on Parallel Processing (Kyoto, Japan) (ICPP ’19) . Asso- ciation for Computing Machinery, New York, NY, US...

    2019

  11. [20]

    Huang and T

    J.C. Huang and T. Leng. 1999. Generalized loop-unrolling: a method for program speedup. In Proceedings 1999 IEEE Symposium on Application-Specific Systems and Software Engineering and Technology. ASSET’99 (Cat. No.PR00122) . 244–248. https://doi.org/10.1109/ASSET.1999.756775

    1999

  12. [21]

    Saba Jamilan, Tanvir Ahmed Khan, Grant Ayers, Baris Kasikci, and Heiner Litz

  13. [22]

    Shizhi Jiang, Qiusong Yang, and Yiwei Ci. 2022. Merging Similar Patterns for Hard- ware Prefetching. In 2022 55th IEEE/ACM International Symposium on Microarchi- tecture (MICRO). 1012–1026. https://doi.org/10.1109/MICRO56248.2022.00071

    2022

  14. [23]

    Akira Koseki, Hideaki Komastu, and Yoshiaki Fukazawa. 1997. A method for estimating optimal unrolling times for nested loops. In Proceedings of the 1997 International Symposium on Parallel Architectures, Algorithms and Networks (I- SPAN’97). 376–382. https://doi.org/10.1109/IS...

    1997

  15. [24]

    Roland Kühn, Jan Mühlig, and Jens Teubner. 2024. How to Be Fast and Not Furious: Looking Under the Hood of CPU Cache Prefetching. In Proceedings of the 20th International Workshop on Data Management on New Hardware (Santiago, AA, Chile) (DaMoN ’24). Association for Computing M...

    2024

  16. [25]

    Snehasish Kumar, Arrvindh Shriraman, Vijayalakshmi Srinivasan, Dan Lin, and Jordon Phillips. 2014. SQRL: hardware accelerator for collecting software data structures. In Proceedings of the 23rd international conference on Parallel architec- tures and compilation (PACT ’14). AC...

    2014

  17. [26]

    Jaekyu Lee, Hyesoon Kim, and Richard Vuduc. 2012. When Prefetching Works, When It Doesn’t, and Why. ACM Trans. Archit. Code Optim. 9, 1, Article 2 (March 2012), 29 pages. https://doi.org/10.1145/2133382.2133384

    2012

  18. [27]

    Tzu-Mao Li, Michaël Gharbi, Andrew Adams, Frédo Durand, and Jonathan Ragan- Kelley. 2018. Differentiable programming for image processing and deep learning in halide. ACM Trans. Graph. 37, 4, Article 139 (July 2018), 13 pages. https: //doi.org/10.1145/3197517.3201383

    2018

  19. [28]

    2016.PolyBench/C

    Tomofumi Yuki Louis-Noel Pouchet, Uday Bondugula. 2016.PolyBench/C. Version 4.2

    2016

  20. [29]

    Shengbai Luo, Bo Wang, Yihao Shi, Xueyi Zhang, Qingshan Xue, and Sheng Ma

  21. [30]

    Gabriel Marin, Collin McCurdy, and Jeffrey S. Vetter. 2013. Diagnosis and opti- mization of application prefetching performance. In Proceedings of the 27th inter- national ACM conference on International conference on supercomputing (ICS’13) . ACM, 303–312. https://doi.org/10....

    2013

  22. [31]

    Francesc Martínez Palau, Marti Torrents, Adrià Armejach, and Marc Casas. 2024. Exploiting Vector Code Semantics for Efficient Data Cache Prefetching. In Pro- ceedings of the 38th ACM International Conference on Supercomputing (Kyoto, Japan) (ICS ’24). Association for Computing...

    2024

  23. [32]

    McCalpin

    John D. McCalpin. 1991-2007. STREAM: Sustainable Memory Bandwidth in High Performance Computers. Technical Report. University of Virginia, Charlottesville, Virginia. http://www.cs.virginia.edu/stream/ A continually updated technical report. http://www.cs.virginia.edu/stream/

    1991

  24. [33]

    McCalpin

    John D. McCalpin. 1995. Memory Bandwidth and Machine Balance in Current High Performance Computers. IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter (Dec. 1995), 19–25

    1995

  25. [34]

    Sanyam Mehta, Rajat Garg, Nishad Trivedi, and Pen-Chung Yew. 2016. TurboTil- ing: Leveraging prefetching to boost performance of tiled codes. InProceedings of the 2016 International Conference on Supercomputing (Istanbul, Turkey) (ICS ’16). Association for Computing Machinery,...

    2016

  26. [35]

    Pierre Michaud. 2016. Best-offset hardware prefetching. In2016 IEEE International Symposium on High Performance Computer Architecture (HPCA) . 469–480. https: //doi.org/10.1109/HPCA.2016.7446087

    2016

  27. [36]

    Mowry and Anoop Gupta

    Todd C. Mowry and Anoop Gupta. 1991. Tolerating latency through software- controlled prefetching in shared-memory multiprocessors. J. Parallel and Distrib. Comput. 12, 2 (1991), 87–106. https://doi.org/10.1016/0743-7315(91)90014-Z

    1991 doi

  28. [37]

    Mowry, Monica S

    Todd C. Mowry, Monica S. Lam, and Anoop Gupta. 1992. Design and evaluation of a compiler algorithm for prefetching. SIGPLAN Not. 27, 9 (Sept. 1992), 62–73. https://doi.org/10.1145/143371.143488

    1992

  29. [38]

    Ravi Teja Mullapudi, Andrew Adams, Dillon Sharlet, Jonathan Ragan-Kelley, and Kayvon Fatahalian. 2016. Automatically scheduling halide image processing pipelines. ACM Trans. Graph. 35, 4, Article 83 (July 2016), 11 pages. https: //doi.org/10.1145/2897824.2925952

    2016

  30. [39]

    Nesbit and James E

    Kyle J. Nesbit and James E. Smith. 2004. Data Cache Prefetching Using a Global History Buffer. In 10th International Symposium on High Performance Computer Architecture (HPCA’04). 96–96. https://doi.org/10.1109/HPCA.2004.10030

    2004 arXiv

  31. [40]

    Biswabandan Panda. 2024. The Game of Latency, Bandwidth, and Hardware Prefetching. Computer 57, 6 (2024), 122–126. https://doi.org/10.1109/MC.2024. 3384851

    2024 doi

  32. [41]

    Biswabandan Panda and Shankar Balachandran. 2016. Expert Prefetch Prediction: An Expert Predicting the Usefulness of Hardware Prefetchers. IEEE Computer Architecture Letters 15, 1 (2016), 13–16. https://doi.org/10.1109/LCA.2015.2428703

    2016

  33. [42]

    Jonathan Ragan-Kelley, Connelly Barnes, Andrew Adams, Sylvain Paris, Frédo Durand, and Saman Amarasinghe. 2013. Halide: a language and compiler for optimizing parallelism, locality, and recomputation in image processing pipelines. In Proceedings of the 34th ACM SIGPLAN Confere...

    2013

  34. [43]

    Saami Rahman, Martin Burtscher, Ziliang Zong, and Apan Qasem. 2015. Maxi- mizing Hardware Prefetch Effectiveness with Machine Learning. In 2015 IEEE 17th International Conference on High Performance Computing and Communica- tions, 2015 IEEE 7th International Symposium on Cyber...

    2015 doi

  35. [44]

    Vivek Sarkar. 2000. Optimized unrolling of nested loops. In Proceedings of the 14th International Conference on Supercomputing (Santa Fe, New Mexico, USA) (ICS ’00). Association for Computing Machinery, New York, NY, USA, 153–166. https://doi.org/10.1145/335231.335246

    2000

  36. [45]

    Kozuch, and Todd C

    Vivek Seshadri, Onur Mutlu, Michael A. Kozuch, and Todd C. Mowry. 2012. The evicted-address filter: a unified mechanism to address both cache pollution and thrashing. In Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques (Minn...

    2012

  37. [46]

    Savvas Sioutas, Sander Stuijk, Henk Corporaal, Twan Basten, and Lou Somers

  38. [47]

    Alan J. Smith. 1978. Sequential Program Prefetching in Memory Hierarchies. Computer 11, 12 (1978), 7–21. https://doi.org/10.1109/C-M.1978.218016

    1978

  39. [48]

    Tambat and S

    S. Tambat and S. Vajapeyam. 2002. Page-Level Behavior of Cache Contention. IEEE Computer Architecture Letters 1, 1 (2002), 9–9. https://doi.org/10.1109/L- CA.2002.9

    2002 doi

  40. [49]

    Vanderwiel and David J

    Steven P. Vanderwiel and David J. Lilja. 2000. Data prefetch mechanisms. ACM Comput. Surv. 32, 2 (June 2000), 174–199. https://doi.org/10.1145/358923.358939

    2000

  41. [50]

    Vanderwijngaart and William Saphir

    Rob F. Vanderwijngaart and William Saphir. 1998. On the Efficacy of Source Code Optimizations for Cache-Based Systems. In NASA Technical Reports Server (NTRS)

    1998

  42. [51]

    Burger, K.S

    Zhenlin Wang, D. Burger, K.S. McKinley, S.K. Reinhardt, and C.C. Weems. 2003. Guided region prefetching: a cooperative hardware/software approach. (2003), 388–398. https://doi.org/10.1109/ISCA.2003.1207016

    2003 arXiv

  43. [52]

    Wolf, Dror E

    Michael E. Wolf, Dror E. Maydan, and Ding-Kai Chen. 1996. Combining loop transformations considering caches and scheduling. In Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29 . 274–

    1996

  44. [53]

    Yuan Zhao and Ken Kennedy. 2005. Scalarization Using Loop Alignment and Loop Skewing. The Journal of Supercomputing 31, 1 (Jan. 2005), 5–46. https: //doi.org/10.1023/b:supe.0000049323.47732.02

    2005

  45. [286]

    https://doi.org/10.1109/MICRO.1996.566468

    1996

  46. [2009]

    In Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA

    In-Core Optimization of High-Order Stencil Computations.. In Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA. Citeseer, 533–538

  47. [2018]

    https://doi.org/10.1145/3168823

    Loop transformations leveraging hardware prefetching, In Proceedings of the 2018 International Symposium on Code Generation and Optimization. https://doi.org/10.1145/3168823

    2018 doi

  48. [2022]

    In Proceedings of the Seventeenth European Conference on Computer Systems (Rennes, France) (EuroSys ’22)

    APT-GET: profile-guided timely software prefetching. In Proceedings of the Seventeenth European Conference on Computer Systems (Rennes, France) (EuroSys ’22). Association for Computing Machinery, New York, NY, USA, 747–764. https: //doi.org/10.1145/3492321.3519583

  49. [2023]

    In Proceedings of the 35th ACM Symposium on Parallelism in Algorithms and Archi- tectures (Orlando, FL, USA) (SPAA ’23)

    An Associativity Threshold Phenomenon in Set-Associative Caches. In Proceedings of the 35th ACM Symposium on Parallelism in Algorithms and Archi- tectures (Orlando, FL, USA) (SPAA ’23). Association for Computing Machinery, New York, NY, USA, 117–127. https://doi.org/10.1145/35...

  50. [2024]

    In 2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP)

    Sparm: A Sparse Matrix Multiplication Accelerator Supporting Multiple Dataflows. In 2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP). 122–130. https://doi.org/10.1109/ ASAP61560.2024.00034

    2024

Pith tools

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