APEIRON: composing smart TDAQ systems for high energy physics experiments

Alessandro Lonardo; Andrea Biagioni; Andrea Ciardiello; Carlotta Chiarini; Cristian Rossi; Francesca Lo Cicero; Francesco Simula; Matteo Turisini; Michele Martinelli; Ottorino Frezza

arxiv: 2607.02429 · v1 · pith:SQN2KP2Lnew · submitted 2026-07-02 · ⚛️ physics.ins-det · cs.AR

APEIRON: composing smart TDAQ systems for high energy physics experiments

Roberto Ammendola , Andrea Biagioni , Carlotta Chiarini , Andrea Ciardiello , Paolo Cretaro , Ottorino Frezza , Francesca Lo Cicero , Alessandro Lonardo

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Michele Martinelli Pier Stanislao Paolucci Pierpaolo Perticaroli Cristian Rossi Francesco Simula Matteo Turisini Piero Vicini

This is my paper

Pith reviewed 2026-07-03 02:32 UTC · model grok-4.3

classification ⚛️ physics.ins-det cs.AR

keywords APEIRONTDAQmulti-FPGAHigh-Level Synthesisdataflow programminghigh energy physicsparticle identificationNA62 experiment

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The pith

APEIRON is a framework that unifies hardware architecture and software stack for multi-FPGA smart TDAQ systems in high energy physics.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces APEIRON as a distributed heterogeneous processing framework that covers both the hardware for multi-FPGA setups and the full software hierarchy. It ranges from low-level device drivers up to a high-level dataflow programming model built on High-Level Synthesis. The approach is illustrated with a particle identification application for the NA62 experiment. A sympathetic reader would care because it aims to make the construction of real-time trigger and data acquisition systems more accessible for physics experiments that demand low latency and high reliability.

Core claim

APEIRON comprises both hardware architecture and software stack for multi-FPGA systems targeting smart TDAQ in high energy physics, spanning the full software hierarchy from low-level device drivers to a high-level dataflow programming model based on High-Level Synthesis, with a particle identification application for the NA62 experiment as a representative physics use case.

What carries the argument

The APEIRON dataflow programming model based on High-Level Synthesis, which composes applications across the entire software hierarchy for heterogeneous multi-FPGA processing.

If this is right

TDAQ systems can be developed and composed using high-level descriptions instead of manual low-level coding.
Heterogeneous multi-FPGA setups become programmable through a consistent stack from drivers to dataflow models.
Particle identification and similar real-time tasks in experiments like NA62 can run within the same unified framework.
The design supports distributed processing while targeting the strict timing constraints of high energy physics triggers.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

Development time for new TDAQ applications in future experiments could shorten if the high-level model scales without per-hardware retuning.
The same structure might apply to other real-time sensor data pipelines outside particle physics if latency targets align.
Testing the framework on larger FPGA clusters would reveal whether communication overhead stays manageable at scale.
Integration points with existing experiment control software could determine how quickly APEIRON sees adoption in running facilities.

Load-bearing premise

A single unified framework using high-level synthesis for the full software hierarchy can meet the real-time performance, latency, and reliability requirements of smart TDAQ systems without extensive custom low-level optimizations.

What would settle it

A direct measurement on the NA62 particle identification task showing that the APEIRON implementation exceeds required latency bounds or drops events under full experimental data rates.

Figures

Figures reproduced from arXiv: 2607.02429 by Alessandro Lonardo, Andrea Biagioni, Andrea Ciardiello, Carlotta Chiarini, Cristian Rossi, Francesca Lo Cicero, Francesco Simula, Matteo Turisini, Michele Martinelli, Ottorino Frezza, Paolo Cretaro, Piero Vicini, Pierpaolo Perticaroli, Pier Stanislao Paolucci, Roberto Ammendola.

**Figure 1.** Figure 1: Data-stream recombination across specialised processing stages in a trigger or datareduction pipeline built with APEIRON. The scalability of this scheme rests on the network infrastructure: a packet-switched, dimension-order-routed mesh whose physical topology can be tailored to the application through configuration rather than redesign. The network constitutes the core enabling element of the platform, b… view at source ↗

**Figure 2.** Figure 2: Schematic of intra-node (red) and inter-node (green: receive; blue: send) data paths between HLS kernels. Inter-node transfers between kernels residing on different FPGAs, carried over high-speed serial transceivers and routed by the network. Routing and switching. The Routing IP contains a crossbar switch, configuration/status registers and the inter-node and intra-node interfaces. Paths across the switch… view at source ↗

**Figure 3.** Figure 3: Dispatcher/Aggregator pair interfacing Intra-node Port 0 to the associated HLS task. Individual message-input FIFOs are selected by the ch id API parameter [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

**Figure 4.** Figure 4: Communication IP connecting HLS kernels (yellow ovals) through data-stream I/O and inter-kernel messaging [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗

**Figure 6.** Figure 6: Topology of the dense neuralnetwork model (64 × 16 × 4) [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗

read the original abstract

We present APEIRON, a distributed heterogeneous processing framework comprising both hardware architecture and software stack for multi-FPGA systems. Targeting smart trigger and data acquisition (TDAQ) systems in high energy physics, APEIRON spans the full software hierarchy: from low-level device drivers to a high-level dataflow programming model based on High-Level Synthesis. We describe the framework design, its core communication infrastructure, and a particle identification application for the NA62 experiment as a representative physics use case.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

APEIRON lays out a unified TDAQ framework architecture for multi-FPGA HEP systems but supplies no performance numbers to check if it meets real-time needs.

read the letter

The main takeaway is that this paper describes APEIRON as a full hardware-plus-software stack for building smart trigger and data acquisition systems on distributed FPGAs. It goes from low-level drivers up through a high-level dataflow model built on High-Level Synthesis, and it illustrates the approach with a particle identification task from the NA62 experiment. The architecture itself is presented in enough detail to see how the pieces are meant to fit together.

What the work does reasonably well is show one way to reduce the usual fragmentation between layers. Experiment teams often end up maintaining separate code bases for drivers, communication, and algorithm implementation; a single framework that spans them could cut down on that overhead. Basing the upper layer on HLS is a sensible choice for this community, where FPGAs are already in use but high-level entry points remain limited.

The clear limitation is the lack of any measured results. The manuscript gives the design and the NA62 use case but no latency figures, throughput numbers, resource counts, or error rates under realistic trigger conditions. That leaves the central question unanswered: whether the high-level approach actually satisfies the sub-microsecond timing and reliability constraints that motivate the work, or whether undisclosed low-level tuning was required. The stress-test note is accurate on this point.

The paper will mainly interest instrumentation groups already working on multi-FPGA TDAQ setups who are looking for structural ideas rather than a ready-to-deploy solution. A reader who needs proven performance numbers will have to wait for follow-up measurements. It is still worth sending to peer review; the design choices look coherent and the community could usefully comment on whether the stack is practical once some benchmarks are added.

Referee Report

1 major / 0 minor

Summary. The paper presents APEIRON, a distributed heterogeneous processing framework for multi-FPGA systems targeting smart TDAQ in high energy physics. It comprises hardware architecture and a full software stack spanning low-level device drivers to a high-level dataflow programming model based on High-Level Synthesis, with a particle identification application for the NA62 experiment as a representative use case.

Significance. A validated unified HLS-based stack for multi-FPGA TDAQ could reduce custom low-level development effort in HEP experiments, but without any reported performance metrics the practical significance cannot be assessed.

major comments (1)

[Abstract / NA62 use case] Abstract and NA62 use-case description: the central claim that APEIRON is suitable for real-time smart TDAQ systems rests on the assertion that the HLS dataflow model meets sub-microsecond latency and high-throughput requirements, yet the manuscript supplies no measured end-to-end latency, event rate, resource utilization, or error-rate figures for the NA62 particle-ID implementation under realistic trigger conditions.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the detailed review and constructive feedback. We address the single major comment below.

read point-by-point responses

Referee: [Abstract / NA62 use case] Abstract and NA62 use-case description: the central claim that APEIRON is suitable for real-time smart TDAQ systems rests on the assertion that the HLS dataflow model meets sub-microsecond latency and high-throughput requirements, yet the manuscript supplies no measured end-to-end latency, event rate, resource utilization, or error-rate figures for the NA62 particle-ID implementation under realistic trigger conditions.

Authors: We agree that the absence of these quantitative metrics limits the ability to assess the framework's practical suitability for real-time TDAQ. The current manuscript focuses on the overall architecture and programming model, with the NA62 application serving as an illustrative use case rather than a fully benchmarked deployment. In the revised version we will add the requested measurements: end-to-end latency, sustained event rate, FPGA resource utilization, and error rates for the particle-ID kernel, obtained under trigger conditions representative of NA62. revision: yes

Circularity Check

0 steps flagged

No circularity: purely descriptive systems paper with no derivations or predictions

full rationale

The manuscript presents an architectural framework (APEIRON) for multi-FPGA TDAQ systems, including drivers, communication infrastructure, and an HLS-based dataflow model, illustrated by an NA62 particle-ID use case. No equations, fitted parameters, predictions, or first-principles derivations appear in the provided text. The central claim is the existence and design of the framework itself; it does not reduce any result to its own inputs by construction, self-citation chains, or renaming. This is a standard honest finding for an engineering-description paper.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

No free parameters, axioms, or invented entities are described in the abstract; the contribution is a system framework presentation.

pith-pipeline@v0.9.1-grok · 5659 in / 1235 out tokens · 34361 ms · 2026-07-03T02:32:04.399392+00:00 · methodology

discussion (0)

Reference graph

Works this paper leans on

12 extracted references · 12 canonical work pages

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