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REVIEW 4 major objections 6 minor 25 references

E2ESlack: An End-to-End Graph-Based Framework for Pre-Routing Slack Prediction

T0 review · 4 major / 6 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read E2ESlack claims to be the first framework that predicts path-level timing slacks before routing, from placement-stage circuit data, with TNS/WNS close to post-routing static timing analysis and up to 23x runtime savings.

desk verdict A genuinely useful RAT estimation module under ideal AT, but the end-to-end slack claim is untested and the abstract overstates it. read the letter →

arxiv 2501.07564 v2 pith:SYNDHYT5 submitted 2025-01-13 cs.LG

Saurabh Bodhe , Zhanguang Zhang , Atia Hamidizadeh , Shixiong Kai , Yingxue Zhang , Mingxuan Yuan This is my paper · ORCID
classification cs.LG
keywords pre-routingslackpredictionrequiredarrivaltimeestimationgraphneuralnetworkstatictiminganalysisTNS/WNSclosureplacement-stageEDA
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

E2ESlack tries to establish that circuit timing quality—the total and worst negative slack (TNS/WNS) metrics that decide whether a chip meets its clock constraints—can be obtained before routing, using placement-stage circuit files and design constraints. The method combines a parser that turns standard circuit formats into pin-level graphs, a graph-neural-network arrival-time predictor, and a new fast algorithm for estimating required arrival time (RAT). With RAT available, setup slack is computed as RAT minus arrival time, and TNS/WNS follow by aggregating negative-slack endpoints. The authors report that their RAT estimates are more accurate than pre-routing static timing analysis and an adapted prior AT-model baseline, and that the overall pipeline produces TNS/WNS close to post-routing STA while saving up to 23x runtime. If this holds, designers could catch timing violations and iterate on placement long before the expensive routing step.

What carries the argument

The load-bearing mechanism is the RAT estimation module: an algorithm that converts SDC timing constraints and predicted arrival times into a required arrival time for every timing endpoint. For a primary output, endpoint RAT is set to the clock period minus the specified output delay and clock uncertainty; for a register endpoint, the early clock-path delay is estimated from the predicted arrival time at the flip-flop's clock pin, and a clock-reconvergence pessimism correction is added—the difference between the maximum and minimum delay of the common launch-and-capture clock path—but only after a cheap negative-slack path traversal. This yields slack = RAT − AT at each endpoint and therefore TNS/WNS, closing the gap that earlier arrival-time-only predictors left open. The framework also includes a graph parser that turns standard placement, netlist, and library files into pin-node graphs with timing lookup-table features, with variable-sized lookup tables interpolated to a fixed size.

What would settle it

Re-run the TNS/WNS evaluation on the same test circuits using the framework's predicted arrival-time values instead of the post-routing STA labels; if TNS errors become comparable in magnitude to the true negative slacks, or if the set of predicted critical paths diverges from ground truth, the end-to-end pre-routing slack claim would be refuted.

Watch

Extended reading notes

Core claim

The central claim is that path-level slack prediction at the pre-routing stage is achievable end-to-end: given a placed but unrouted circuit, the framework constructs a heterogeneous pin-level graph, predicts arrival times with a timing-engine-inspired graph neural network, and estimates required arrival times at every endpoint from the clock period, SDC constraints, and predicted arrivals on clock pins. It then computes setup slack as RAT minus arrival time, identifies negative-slack critical paths, adds a clock-reconvergence-pessimism correction for those paths, and aggregates the results into TNS and WNS. The authors state that this is the first work addressing pre-routing RAT estimation and path-level slack prediction, and they report a test-set RAT mean absolute error of 0.6454 versus 1.5165 for pre-routing STA and 8.1608 for the adapted prior arrival-time model. They also report TNS/WNS values close to post-routing STA and up to 23x runtime savings. As the paper explicitly notes, the RAT and TNS/WNS numbers are computed using ground-truth post-routing arrival-time labels, so those results assume the arrival-time prediction model is ideal.

Load-bearing premise

The paper's headline RAT and TNS/WNS numbers are calculated using true post-routing arrival times rather than the framework's own predicted arrivals, so the end-to-end accuracy claim rests on the unverified assumption that arrival-time prediction errors are small enough not to change the slack conclusions.

Editorial extensions

If this is right

  • Designers can obtain early TNS/WNS estimates during placement, before routing, and use them to decide whether a design should be sent to the expensive routing step.
  • Any future arrival-time prediction model can be plugged into the framework; the RAT module turns predicted arrival times into path-level slack, so improvements in arrival-time accuracy directly improve RAT and TNS/WNS estimates.
  • RAT estimation is faster and more accurate than pre-routing STA on the tested circuits, meaning a pre-routing STA step can be replaced by the graph-based estimate.
  • The framework reduces the time needed to obtain TNS/WNS metrics by up to 23x compared with routing plus post-routing STA, enabling faster design iterations and earlier timing-closure decisions.
  • Because the paper reports that TNS prediction accumulates error across many paths while WNS tracks more closely, TNS estimates are best treated as a screening signal rather than exact signoff numbers.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial extension: if the ideal-arrival-time assumption holds, the most natural next step is to use E2ESlack inside a placement-optimization loop as a cheap timing surrogate, since the reported 23x saving makes it fast enough to evaluate many placement candidates.
  • Editorial extension: the paper leaves untested whether the RAT estimates remain accurate under early/hold corner analysis, multi-clock or gated-clock designs, or process corners beyond the late-rise setup corner; these are natural stress tests for the algorithm.
  • Editorial extension: an end-to-end validation using the framework's own predicted arrival times, rather than post-routing STA labels, would be needed to know whether the reported TNS/WNS closeness persists; the authors' own assumption of an ideal AT predictor marks the boundary between the pipeline as described and the pipeline as evaluated.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper proposes E2ESlack, an end-to-end framework for pre-routing slack prediction. It consists of a distributed TimingParser that converts LIB/SDF/DEF files into DGL graphs, a GNN-based arrival time (AT) prediction model based on TimingPredict, and a deterministic RAT estimation algorithm that computes endpoint RATs from the clock period, SDC constraints, clock-path delays, and clock reconvergence pessimism (CRPR). From predicted AT and estimated RAT, the framework computes endpoint slacks and TNS/WNS. The authors evaluate AT prediction R2, RAT MAE against modified TimingPredict and pre-routing STA, TNS/WNS against post-routing STA, and runtime speedup. A central caveat stated in Section 3.3 is that all RAT/TNS/WNS results use ground-truth post-routing AT labels rather than the framework's own AT predictions.

Significance. If the claimed performance held for the actual end-to-end pipeline, this would be a practically useful shift-left tool: pre-routing TNS/WNS indicators at large runtime savings would enable earlier timing closure iterations. The modular parser and the CRPR-aware RAT estimation idea are useful contributions, and the runtime comparison includes full pipeline steps that prior work neglected. However, the main claim is currently not supported by the experiments, because accuracy is measured under an ideal-AT assumption while runtime is measured on the full pipeline; moreover, even under that assumption the TNS/WNS agreement is poor on several circuits.

major comments (4)
  1. [Section 3.3, Tables 3 and 4] The central claim that E2ESlack achieves TNS/WNS values comparable to post-routing STA is not tested with the framework's own AT predictions. The paper states verbatim that RAT/TNS/WNS results use AT labels from post-routing STA and assume the AT prediction model is ideal. Since slack is defined as RAT minus AT_pred, the end-to-end claim requires the predicted AT to be accurate at critical endpoints; no experiment reports TNS/WNS with predicted AT. Thus Tables 3 and 4 validate the RAT formula conditional on perfect AT, not the proposed end-to-end framework.
  2. [Table 4] Even under the ideal-AT assumption, the TNS/WNS results do not support the claim of comparability to post-routing STA. For des, TNS is -1945.19 versus -18.41 and WNS is -5.62 versus -1.18; for y_huff, TNS is -5.17 versus 0.00; for xtea, TNS is -15.13 versus -1.14. These are order-of-magnitude TNS discrepancies and WNS errors of several nanoseconds. The low average RAT MAE in Table 3 does not preclude large errors on the few endpoints that determine TNS/WNS, because MAE is averaged over all endpoints. The paper should report per-endpoint slack error distributions and critical-endpoint error statistics.
  3. [Section 5.1, Table 3] The RAT comparison is not apples-to-apples: "Ours" uses ground-truth post-routing AT labels, while the modified TimingPredict baseline must predict RAT from circuit features and the pre-routing STA baseline uses no routing parasitics. The claimed 57.4% average MAE reduction is therefore a comparison of an oracle-assisted formula against prediction/tool baselines. A fair comparison would feed the same information, such as predicted AT from TimingPredict, into all RAT estimators, or would at minimum report RAT MAE conditional on predicted AT.
  4. [Section 5.3 versus Section 3.3] The runtime experiment measures the full pipeline including parser, AT prediction, and RAT estimation, but the accuracy experiment assumes an ideal AT model. Consequently, no single configuration is shown to simultaneously achieve the reported accuracy and the 23x speedup. The "comparable accuracy with 23x runtime" claim in the abstract and introduction mixes two different evaluation setups.
minor comments (6)
  1. [Section 2.1] The paper only considers late/setup slack, but the abstract and title use the unqualified term "slack prediction"; please state the corner limitation in the abstract or contributions.
  2. [Section 3.3] The formulas for RAT_PO and RAT_S in the text are poorly typeset and the treatment of the setup time term Tsu is confusing: it is mentioned in the text but then ignored in the estimation. Please rewrite these definitions in a clear equation block and justify the approximation quantitatively.
  3. [Table 3] The speedup column shows "0x" for several small circuits; please clarify whether this means less than 1x speedup, rounding, or a missing value.
  4. [Section 4.2] No URL or repository link is provided for the new OpenLane benchmark circuits or the exact train/test split; without this information the results are hard to reproduce.
  5. [References] The ACM reference format line "InProceedings of (Arxiv)" is malformed and should be corrected.
  6. [Section 5.1] The phrase "modified TimingPredict" is used for a model that is retrained to predict RAT in addition to AT; please define this modification precisely, including the loss function and training setup, before using it as a baseline.

Circularity Check

1 steps flagged · score 6.0 of 10

TNS/WNS 'prediction' is computed from ground-truth post-routing AT labels, so the end-to-end claim is untested and partially circular by construction.

  1. fitted input called prediction [Section 3.3, paragraph following Algorithm 1; results in Section 5.2, Table 4]
    "It is important to note that when presenting RAT/TNS/WNS results of our algorithm in Table 4 and Table 3 we use AT labels (from post-routing STA) instead of predicted AT from TimingPredict. That is, we assume that the AT prediction model is ideal. This ensures that the results presented for RAT estimation are independent of the performance of the AT prediction model."

    Algorithm 1 defines Slack(endpoint) = RAT(endpoint) – AT_pred(endpoint) and then computes TNS/WNS from these slacks. In the experiments, AT_pred is replaced by post-routing STA AT labels. OpenSTA's ground-truth TNS/WNS is computed from the same post-routing AT labels. Therefore the reported 'Ours' TNS/WNS and the ground truth share the identical AT term; the comparison only measures how closely the RAT formula approximates OpenSTA RAT, not whether the full pre-routing E2ESlack pipeline predicts timing from raw circuit data.

full rationale

The RAT estimation module itself is not circular: it is a deterministic formula using SDC constraints, clock-path delays, and CRPR, with no fitted parameters, so its comparison against pre-routing STA and a modified TimingPredict baseline is a legitimate (though label-leaked) evaluation of RAT estimation under an explicitly stated ideal-AT assumption. The circularity lies in the central end-to-end claim. Because Table 4 substitutes post-routing STA AT labels for the framework's own AT predictions, and because ground-truth TNS/WNS is also computed from those same AT labels, the reported agreement is forced by the shared input: the AT component cancels from the comparison, leaving only the RAT approximation error. This does not validate the actual E2ESlack pipeline, whose AT prediction error could change the sign of marginal slacks and strongly affect WNS/TNS. The paper is transparent about the substitution, but the abstract's headline claim that the framework achieves TNS/WNS comparable to post-routing STA is supported only under an idealized assumption that is never tested. No load-bearing self-citation or externally imported uniqueness argument was found; the self-citations to PreRoutGNN and prior graph models are not used to justify the derivation.

Assumptions & free parameters 1 free parameters · 5 assumptions · 0 invented entities

The RAT estimation formula is a standard STA relation with no fitted parameters, but it borrows the AT values from an external GNN model whose weights are not part of this paper's contribution. The evaluation protocol further assumes ideal AT, which is the main epistemic debt.

free parameters (1)
  • TimingPredict GNN weights = pretrained weights, not released
    The framework's AT predictions come from this external model; its accuracy is not measured in the end-to-end slack results.
assumptions (5)
  • ad hoc to paper The minimum early clock path delay to a synchronous element can be approximated by the predicted AT at its CLK pin.
    Section 3.3, RAT_S = T + D_S^E - mu + CRP; D_S^E is estimated from predicted AT at CLK pin, which mixes early/late and data/clock semantics.
  • domain assumption Cell setup time T_su is negligible and ignored.
    Section 3.3: 'Since it is usually small we ignore it in our estimation in interest of runtime.'
  • domain assumption CRP only needs to be computed on paths with negative slack; uncorrected RAT identifies all critical paths.
    Section 3.3: CRP >= 0, so it cannot create new critical paths; this is mathematically sound.
  • domain assumption The graph representation and AT model from TimingPredict are adopted without modification.
    Section 3.1: 'we choose to use a representation identical to the one proposed in that work.'
  • ad hoc to paper The AT prediction model is assumed ideal when evaluating RAT and TNS/WNS.
    Section 3.3: 'we assume that the AT prediction model is ideal.' This is an evaluation assumption, not a modeling axiom, but it is load-bearing for the accuracy claims.

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Cite this review

Pith. "Pith review of E2ESlack: An End-to-End Graph-Based Framework for Pre-Routing Slack Prediction." pith.science (2026). https://pith.science/paper/SYNDHYT5

@misc{pith2026250107564,
  author       = {Pith},
  title        = {Pith review of: E2ESlack: An End-to-End Graph-Based Framework for Pre-Routing Slack Prediction},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/SYNDHYT5}},
  note         = {Machine review of arXiv:2501.07564}
}
read the original abstract

Pre-routing slack prediction remains a critical area of research in Electronic Design Automation (EDA). Despite numerous machine learning-based approaches targeting this task, there is still a lack of a truly end-to-end framework that engineers can use to obtain TNS/WNS metrics from raw circuit data at the placement stage. Existing works have demonstrated effectiveness in Arrival Time (AT) prediction but lack a mechanism for Required Arrival Time (RAT) prediction, which is essential for slack prediction and obtaining TNS/WNS metrics. In this work, we propose E2ESlack, an end-to-end graph-based framework for pre-routing slack prediction. The framework includes a TimingParser that supports DEF, SDF and LIB files for feature extraction and graph construction, an arrival time prediction model and a fast RAT estimation module. To the best of our knowledge, this is the first work capable of predicting path-level slacks at the pre-routing stage. We perform extensive experiments and demonstrate that our proposed RAT estimation method outperforms the SOTA ML-based prediction method and also pre-routing STA tool. Additionally, the proposed E2ESlack framework achieves TNS/WNS values comparable to post-routing STA results while saving up to 23x runtime.

Figures

Figures reproduced from arXiv: 2501.07564 by the authors.

Figure 1
Figure 1. Framework Architecture. Blue arrows indicate the workflow for label generation, which is only required for training. [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗

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Reference graph

Works this paper leans on

25 extracted references · 23 canonical work pages

  1. [1]

    Erick Carvajal Barboza, Nishchal Shukla, Yiran Chen, and Jiang Hu. 2019. Ma- chine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism. In Proceedings of the 56th Annual Design Automation Conference 2019 (Las Vegas, NV, USA) (DAC ’19). Association for Computing Machinery, New York, NY, USA, Article 106, 6 pages. https://doi.org/10.1145/331...

    arXiv 2019

  2. [2]

    Vivek Bhardwaj. 2021. Shift left trends for design convergence in soc: An eda perspective. Vivek Bhardwaj. Shift Left Trends for Design Convergence in SOC: An EDA Perspective. International Journal of Computer Applications (2021)

    work page 2021

  3. [3]

    Wei-Ting J Chan, Kun Young Chung, Andrew B Kahng, Nancy D MacDonald, and Siddhartha Nath. 2016. Learning-based prediction of embedded memory timing failures during initial floorplan design. In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 178–185

    work page 2016

  4. [4]

    James Cherry. 2024. OpenSTA, Parallax Software. https://github.com/parallaxsw/ OpenSTA

    work page 2024

  5. [5]

    James Cherry. 2024. OpenSTA User Manual. https://github.com/The-OpenROAD- Project/OpenSTA/blob/master/doc/OpenSTA.pdf. pages 61, 78

    work page 2024

  6. [6]

    Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, and Zhiyao Xie. 2023. MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)

    work page 2023

  7. [7]

    Eby G Friedman. 2001. Clock distribution networks in synchronous digital integrated circuits. Proc. IEEE (2001). E2ESlack: An End-to-End Graph-Based Framework for Pre-Routing Slack Prediction Arxiv, 2024, Montreal, Canada

    work page 2001

  8. [8]

    Zizheng Guo. 2021. OpenSTADump. https://github.com/TimingPredict/ OpenSTADump

    work page 2021

Show all 25 references
  1. [9]

    Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z Pan, and Yibo Lin

  2. [10]

    Seung-Soo Han, Andrew B Kahng, Siddhartha Nath, and Ashok S Vydyanathan

  3. [11]

    Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Wenbin Xu, Sachin S Sapatnekar, Ramesh Harjani, and Jiang Hu. 2020. A customized graph neural network model for guiding analog IC placement. InProceedings of the 39th International Conference on Computer-Aided Design . 1–9

    2020

  4. [12]

    Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, and Gi-Joon Nam. 2020. Routing-free crosstalk prediction. In Proceedings of the 39th International Conference on Computer-Aided Design . 1–9

    2020

  5. [13]

    Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, and David Z. Pan. 2019. DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. In Proceedings of the 56th Annual Design Automation Conference 2019

    2019

  6. [14]

    Mingjie Liu, Walker J Turner, George F Kokai, Brucek Khailany, David Z Pan, and Haoxing Ren. 2021. Parasitic-aware analog circuit sizing with graph neural networks and Bayesian optimization. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1372–1377

    2021

  7. [15]

    Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, and Chung-Kuan Cheng. 2015. ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov’s Method. ACM Trans. Des. Autom. Electron. Syst. (2015)

    2015

  8. [16]

    Thomas M McWilliams. 1980. Verification of timing constraints on large digital systems. In Proceedings of the 17th Design Automation Conference . 139–147

    1980

  9. [17]

    Jordan, and Ion Stoica

    Philipp Moritz, Robert Nishihara, Stephanie Wang, Alexey Tumanov, Richard Liaw, Eric Liang, Melih Elibol, Zongheng Yang, William Paul, Michael I. Jordan, and Ion Stoica. 2018. Ray: A Distributed Framework for Emerging AI Applications. arXiv:1712.05889 [cs.DC] https://arxiv.org...

    2018 arXiv

  10. [18]

    Prianka Sengupta, Aakash Tyagi, Yiran Chen, and Jiang Hu. 2022. How Good Is Your Verilog RTL Code? A Quick Answer from Machine Learning. In 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

    2022

  11. [19]

    Mohamed Shalan and Tim Edwards. 2020. Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited Paper. In 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD) . 1–6

    2020

  12. [20]

    Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, and Yiran Chen

  13. [21]

    Shuwen Yang, Zhihao Yang, Dong Li, Yingxueff Zhang, Zhanguang Zhang, Guojie Song, and Jianye Hao. 2022. Versatile multi-stage graph neural network for circuit representation. Advances in Neural Information Processing Systems 35 (2022), 20313–20324

    2022

  14. [22]

    Ruizhe Zhong, Junjie Ye, Zhentao Tang, Shixiong Kai, Mingxuan Yuan, Jianye Hao, and Junchi Yan. 2024. Preroutgnn for timing prediction with order preserving partition: Global circuit pre-training, local delay learning and attentional cell modeling. In Proceedings of the AAAI C...

    2024

  15. [2014]

    In 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)

    A deep learning methodology to proliferate golden signoff timing. In 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) . IEEE, 1–6

    2014

  16. [2021]

    In Proceedings of the 26th Asia and South Pacific Design Automation Conference

    Net2: A graph attention network method customized for pre-placement net length estimation. In Proceedings of the 26th Asia and South Pacific Design Automation Conference. 671–677

  17. [2022]

    In Proceedings of the 59th ACM/IEEE Design Automation Conference

    A timing engine inspired graph neural network model for pre-routing slack prediction. In Proceedings of the 59th ACM/IEEE Design Automation Conference . 1207–1212

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Reviewed August 10, 2026 · model on record in the stance chip above.