Paper Citation Record · LEDGER

MLP Aware Scheduling Techniques in Multithreaded Processors

As of 16 August 2026, this Paper Citation Record lists 4 of 4 outbound references and 0 inbound Pith citation observations for arXiv:1908.04236.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
1908.04236 v1

Coverage vector

measured 4 of 4 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-14T13:49:03.141611Z

measured 4 of 4 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-15T06:32:42.880941+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

4 of 4 outbound references displayed

verified exact0
verified fuzzy4
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation cf535ada-d5ee-433b-a00a-91d368706771 · outbound

This paper cites Code Transformations to Improve Memory Parallelism.

MLP Aware Scheduling Techniques in Multithreaded Processors Code Transformations to Improve Memory Parallelism

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T13:49:03.218506Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation b71e4ab7-e685-4f8d-98d8-2c8dd3b425eb · outbound

This paper cites MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor.

MLP Aware Scheduling Techniques in Multithreaded Processors MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T13:49:03.204764Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 29c98ec7-1dcc-498f-8bd1-e6ebefd248e6 · outbound

This paper cites Co-optimizing memory-level parallelism and cache-level parallelism.

MLP Aware Scheduling Techniques in Multithreaded Processors Co-optimizing memory-level parallelism and cache-level parallelism

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T13:49:03.191863Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation cfa4d321-9ec0-4ce9-8cf7-bc7f55bf73d0 · outbound

This paper cites Parallelism-Aware Batch Scheduling: Enhancing Both Performance and Fairness of Shared DRAM Systems.

MLP Aware Scheduling Techniques in Multithreaded Processors Parallelism-Aware Batch Scheduling: Enhancing Both Performance and Fairness of Shared DRAM Systems

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T13:49:03.178736Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Pith citing papers

No inbound Pith citation observations are available.