Paper Citation Record · LEDGER

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study

As of 18 August 2026, this Paper Citation Record lists 29 of 29 outbound references and 0 inbound Pith citation observations for arXiv:2502.10194.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2502.10194 v1

Coverage vector

measured 29 of 29 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-07T19:04:12.770202Z

measured 29 of 29 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-18T06:34:40.430872+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

29 of 29 outbound references displayed

verified exact0
verified fuzzy28
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch1

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 5a471720-cee7-4f5a-92c7-5e6d6331bbb3 · outbound

This paper cites The risc-v instruction set manual volume i: User-level isa document version 20191214-draft„.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study The risc-v instruction set manual volume i: User-level isa document version 20191214-draft„

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:13.088211Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 1a7a2ac4-c445-4ed4-a98a-9bbec0d7831d · outbound

This paper cites The risc-v instruction set manual volume ii: Privileged architecture document version 1.12-draft„.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study The risc-v instruction set manual volume ii: Privileged architecture document version 1.12-draft„

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:13.080535Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 1248858c-49fc-449f-a150-aa1b798a79ac · outbound

This paper cites [online] available: https://riscv.org/.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study [online] available: https://riscv.org/

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:13.063935Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 405fb287-3cdb-4033-b10b-55f520b2d4c2 · outbound

This paper cites Risc-v instruction set architecture extensions: A survey,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Risc-v instruction set architecture extensions: A survey,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:13.056087Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 0e654a24-cdc0-4595-8463-63917097b496 · outbound

This paper cites Risc-v resource-constrained cores: A survey and energy comparison,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Risc-v resource-constrained cores: A survey and energy comparison,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:13.047417Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation c009a83e-a830-457a-a8ea-485e1f2c9304 · outbound

This paper cites Towards automatic property generation for soc se- curity verification,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Towards automatic property generation for soc se- curity verification,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:13.037895Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 3d9a3e5a-e401-49c2-9cc6-40415be5fabb · outbound

This paper cites Ieee standard for system, software, and hardware verification and validation - redline,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Ieee standard for system, software, and hardware verification and validation - redline,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:13.028531Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 7789d229-8ce3-446f-8748-c9ca726dba3b · outbound

This paper cites Accessible formal verification for safety-critical hard- ware design,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Accessible formal verification for safety-critical hard- ware design,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:13.008956Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 51510abb-44be-4bd0-abb0-26e8e7858ed1 · outbound

This paper cites Formal verification of hardware support for advanced encryption standard,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Formal verification of hardware support for advanced encryption standard,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.999180Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 2791afe1-ad25-4779-8f3b-2b64b564c678 · outbound

This paper cites A study on the assertion-based verification of digital ic,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study A study on the assertion-based verification of digital ic,

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.990108Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 3bdbf0b7-99b1-43e5-8955-69936c28b67c · outbound

This paper cites Security and fault diagnosis-based assertion-based verification for fpga,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Security and fault diagnosis-based assertion-based verification for fpga,

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.979921Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 599c8fec-0dda-462e-980e-e9f882b1f553 · outbound

This paper cites Systemverilog assertion based verification of amba- ahb,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Systemverilog assertion based verification of amba- ahb,

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.970127Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 662b1aac-656a-406b-8356-247431f1a5ee · outbound

This paper cites Practical assertion-based formal verification for soc designs,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Practical assertion-based formal verification for soc designs,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.961088Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 2579847a-2aa0-4152-9793-9e7069ebdd6c · outbound

This paper cites Property based formal security verification for hard- ware trojan detection,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Property based formal security verification for hard- ware trojan detection,

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.951575Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 76ca7d16-ca2b-4a55-947c-e1d86a153476 · outbound

This paper cites Fault attacks on access control in processors: Threat, formal analysis and microarchitectural mitigation,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Fault attacks on access control in processors: Threat, formal analysis and microarchitectural mitigation,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.930894Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 5f4179df-21b5-44db-93d9-ef95ac62eeec · outbound

This paper cites Invited: Formal verification of security critical hardware- firmware interactions in commercial socs,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Invited: Formal verification of security critical hardware- firmware interactions in commercial socs,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:13.019184Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation f81c5127-0cee-44ac-bd54-673ae37c86a3 · outbound

This paper cites Formal verification of security properties on risc- v processors,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Formal verification of security properties on risc- v processors,

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.918896Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation b1429969-c8e3-49bd-8fab-aefc7f6d519f · outbound

This paper cites Security verification of risc-v system based on isa level information flow tracking,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Security verification of risc-v system based on isa level information flow tracking,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.942008Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 9d045eee-898c-41f9-9fac-63dcd1084c9a · outbound

This paper cites Formal verification of correctness and information flow security for an in-order pipelined processor,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Formal verification of correctness and information flow security for an in-order pipelined processor,

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.907081Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation ee80e8c5-0e71-413e-a1d7-e7fa7d05eb16 · outbound

This paper cites Transys: Leveraging common security properties across hardware designs,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Transys: Leveraging common security properties across hardware designs,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.895676Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 4c4670b5-5f8e-4bf0-8b5e-3c9445c03f2c · outbound

This paper cites Hardware security in practice: Challenges and opportu- nities,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Hardware security in practice: Challenges and opportu- nities,

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.885421Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 68cfae5a-76ce-49c3-8718-c6a72634bbb4 · outbound

This paper cites Design of a generic security interface for risc-v processors and its applications,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Design of a generic security interface for risc-v processors and its applications,

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.875099Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 59dfa73d-c1bb-4603-a3ad-31545e2fafcf · outbound

This paper cites Reusing verification assertions as security checkers for hardware trojan detection,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Reusing verification assertions as security checkers for hardware trojan detection,

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.863608Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 3c6c13f7-e26c-4780-8e9f-185a1d9f18f0 · outbound

This paper cites Sentaur: Security enhanced trojan assessment using llms against undesirable revisions,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Sentaur: Security enhanced trojan assessment using llms against undesirable revisions,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.852455Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation fd3fbfe8-9588-4d23-b0ff-0988ae10ecda · outbound

This paper cites Systemverilog assertions handbook,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Systemverilog assertions handbook,

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.840316Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation fadda115-5041-4259-8bf7-c2a7760f0365 · outbound

This paper cites Ns31a : Risc-v 32bit cpu which supports iso26262 asil d,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Ns31a : Risc-v 32bit cpu which supports iso26262 asil d,

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.828534Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation cdd2b526-4dbf-40c7-a38a-f5e0cd26b174 · outbound

This paper cites Ibex risc-v core,.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Ibex risc-v core,

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:12.817374Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation d5754130-5f12-4e71-bf1a-fcbdf93f6498 · outbound

This paper cites Available: http://nic.vajn.icu/PDF/GigaDevice/RISCV- Privileged.pdf.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study Available: http://nic.vajn.icu/PDF/GigaDevice/RISCV- Privileged.pdf

Reference 2019

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T19:04:13.072127Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 8c0caccd-7e26-40e4-bfbb-593b5ad1963e · outbound

This paper cites SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions.

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions

Reference 2024

Resolution: metadata mismatch; local_arxiv, observed 2026-08-07T19:04:12.805557Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Pith citing papers

No inbound Pith citation observations are available.