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High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms

T0 review · 3 major / 4 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read By running target ARM software natively through KVM, a SystemC-TLM multicore CPU model replaces the instruction-set simulator and reports 10x to over 100x speedups on ARM hosts.

desk verdict A real, useful engineering contribution—multicore KVM-based SystemC CPU model without perf counters or kernel patches—but the headline speedups are inflated by comparing the ARM machine against a slower x86 host. read the letter →

arxiv 2505.12987 v2 pith:TKLONO3T submitted 2025-05-19 cs.SE

Nils Bosbach , Rebecca Pelke , Niko Zurstra{ss}en , Jan Henrik Weinstock , Lukas Jünger , Rainer Leupers This is my paper · ORCID
classification cs.SE
keywords ARM-on-ARMvirtualizationKVMSystemC-TLMmulticoreCPUmodelvirtualplatforminstruction-setsimulatorWFIannotationtemporaldecoupling
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a multicore SystemC-TLM virtual platform can run target ARM software natively on an ARM host by using Linux's KVM hypervisor, eliminating the instruction-set simulator (ISS) entirely. The CPU model it builds acts as a drop-in replacement for an ISS inside an existing virtual platform, with memory-mapped peripheral accesses trapped by KVM and forwarded to the SystemC simulation. On compute-intensive workloads the platform is reported to run up to 10x faster than an ISS-based reference, and over 100x faster on some benchmarks, while a software watchdog and WFI annotations remove the earlier need for performance counters and custom kernel patches. The outcome matters to anyone doing pre-silicon software development, driver bring-up, or CI/CD testing on ARM targets, where simulation speed is the bottleneck.

What carries the argument

The load-bearing object is the KVM-backed vCPU model embedded in the VCML processor class. For each simulated core, a worker thread calls KVM_RUN to execute target instructions natively on the host; a placeholder SC_THREAD in the SystemC main thread keeps synchronization, and a software-based watchdog thread sends SIGUSR1 to halt KVM_RUN after the wall-clock time corresponding to one quantum. WFI annotation completes the mechanism: the ELF of the target Linux kernel is searched for the cpu_do_idle symbol, a breakpoint is set on the WFI instruction inside it, and when a core reaches the breakpoint the model suspends the core until an interrupt is signaled, skipping idle-loop simulation entirely.

What would settle it

Run the ISS-based A VP64 baseline on the same Apple M2 Pro host used for the ARM-on-ARM measurements and re-measure the Dhrystone and MiBench speedups. If the speedup over a same-host ISS drops well below the reported 10x and 100x figures, most of the gain is host CPU performance rather than native execution through KVM; if the figures roughly hold, the method's claim is confirmed.

Watch

Extended reading notes

Core claim

The central claim is that hardware-assisted virtualization can replace instruction-set simulation inside a SystemC-TLM virtual platform when the host and target share the ARM ISA. Each simulated core is a KVM guest running target software natively; exits from KVM handle MMIO accesses as TLM transactions in the SystemC main thread, and a shared software watchdog bounds each quantum's execution time without relying on hardware performance counters. The paper further shows that idle loops can be skipped by locating the cpu_do_idle symbol in the target kernel's ELF file, placing a breakpoint on its WFI instruction, and suspending the core until an interrupt arrives. On an Apple M2 Pro host, the resulting platform reports up to 10x speedup over the ISS-based A VP64 on parallel Dhrystone and speedups beyond 100x on some MiBench workloads, with a minimum observed speedup of 1.8x across all tested user-space benchmarks.

Load-bearing premise

The speedup figures compare the new platform running on an Apple M2 Pro against the ISS-based baseline running on an AMD Ryzen 9 3900X, with no same-host or speed-normalized comparison; if the host hardware difference accounts for part of the gap, the reported speedups overstate the method's advantage.

Editorial extensions

If this is right

  • Unmodified target ARM operating systems and user-space programs can run natively inside a SystemC-TLM virtual platform, with the KVM-based CPU model serving as a drop-in replacement for the ISS and no other changes to the platform.
  • The approach no longer depends on hardware performance counters or patched kernels, so it works on hosts such as Apple Silicon Linux where standard perf-based guest-instruction counting is unavailable.
  • Combining parallel core execution with WFI annotation brings a multicore Linux boot to under one second for dual- and quad-core configurations, where unannotated sequential boot can take tens of seconds.
  • Speedups are workload-dependent: compute-bound Dhrystone reaches about 10x, small-input MiBench workloads exceed 100x, and communication-heavy NAS benchmarks stay above 1.8x, with the largest gains appearing where dynamic binary translation overhead dominates the ISS baseline.
  • Because KVM exposes only EL0 and EL1 to the guest, the model covers OS and application software but cannot simulate hypervisors at EL2 or trusted firmware at EL3; the authors point to RISC-V-on-RISC-V as the natural next application of the same design.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The reported 10x-to-100x figures are best read as upper bounds: the ARM-on-ARM platform ran on an Apple M2 Pro while the A VP64 ISS baseline ran on an AMD Ryzen 9 3900X, so a same-host ISS comparison would likely narrow the gap; the method's intrinsic advantage is probably a smaller multiple.
  • The ELF-symbol-based WFI annotation is a generalizable pattern: any operating system with a known idle-loop symbol could be annotated the same way, and using debug information to find idle loops automatically would remove the Linux-specific manual step.
  • The largest speedups come from small-input workloads where the ISS's dynamic binary translation cost dominates, which predicts that on long-running, realistic application workloads the advantage will settle near the compute-bound 10x figure rather than the 100x+ outliers.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper presents an ARM-on-ARM approach to CPU modeling in SystemC-TLM virtual platforms. Instead of an instruction-set simulator, the CPU model uses Linux KVM on an ARM host to execute target software natively, trapping MMIO accesses and WFI instructions to maintain interaction with the modeled peripherals. The authors extend this idea to multicore platforms using a parallel execution strategy, replace per-requirement performance-counter-based instruction counting with a software watchdog timer, and introduce WFI annotations by setting breakpoints on the target Linux idle-loop symbol cpu_do_idle. Benchmarks compare the proposed AoA platform with the ISS-based A VP64 on Dhrystone, Linux boot, STREAM, MiBench, and NAS Parallel Benchmarks, claiming up to 10x speedup on compute-intensive workloads and more than 100x on some user-space benchmarks.

Significance. The technique is plausible and well motivated: removing the dependence on custom kernel patches and on specific hardware performance counters is a genuine engineering contribution, and the WFI-annotation workaround is an interesting and practical idea. The implementation is built on open-source components, and the multicore SystemC-TLM CPU model could be a useful drop-in replacement for ISS-based models if the performance claims are substantiated. However, the central quantitative claims are not supported by the data as presented, because the AoA platform and the ISS baseline were benchmarked on different host machines with no same-host or normalized control. The stress-test concern about missing same-host baselines directly lands on the paper's headline results.

major comments (3)
  1. [Section V, Figures 5-7] The central speedup claim compares measurements on different hosts. The AoA platform is benchmarked on an Apple M2 Pro (6 Avalanche and 4 Blizzard cores), while the ISS-based A VP64 baseline runs on an AMD Ryzen 9 3900X, and the reported speedup S is computed as t_A VP64 divided by t_This Work across those two machines. No same-host baseline, normalized comparison, or calibration is reported, so the 'up to 10x' and 'more than 100x' figures conflate the benefit of KVM-based native execution with the M2 Pro's generally higher single-thread and memory performance. The authors should either benchmark both models on the same host (for example, by running A VP64 on the Mac mini under Asahi Linux) or report a hardware-normalized metric using per-host reference benchmarks before the headline speedups can be accepted.
  2. [Section V, Figures 5-7] There are no repeated trials or statistical measures anywhere in the results section. Each reported value appears to be a single measurement, and no error bars, confidence intervals, or variance information are given. Given the large spread of speedups in Figure 7 (from about 1.8x to 165x), the absence of repeated-run statistics makes it impossible to assess whether the reported differences between core counts, quantum values, and parallelization modes are meaningful or within measurement noise. At minimum, the authors should report medians and spreads over several repetitions and state the resolution of the wall-clock timing used.
  3. [Section V-C, Figure 7] The speedups in Figure 7 are attributed primarily to native execution and the overheads of the DBT-based ISS, but the experimental setup also enables WFI annotations for the AoA model and uses A VP64 as the baseline. For the single-threaded MiBench benchmarks, the authors themselves observe that the large speedups on small inputs (up to 165x for Susan S) largely reflect ISS translation caching behavior rather than the raw speed of native execution. This makes the headline 'speedup' a mixture of several factors: host hardware, native KVM execution, WFI annotation, and baseline ISS efficiency. The paper should decompose the contributions, for example by comparing AoA with and without WFI annotations on the same host and against the same baseline configuration.
minor comments (4)
  1. [Abstract] The abstract's phrase 'no special requirements on the host system' overstates the case, since the approach requires an ARM host with virtualization host extensions, Linux, and KVM; it is more accurate to say it requires no custom kernel patches and no special PMU features.
  2. [Figure 7 caption] The legend 'WFI\Cores 1 2 4 8' with entries 'Annotated' and 'KVM-handled' is difficult to parse; the caption should explain what is plotted for each entry and state which configurations use WFI annotations.
  3. [References] Reference [27], cited for the NAS Parallel Benchmarks, points to the 'nasa-jpl/embedded-gcov' repository rather than to the NPB suite; this citation should be corrected.
  4. [Section VI] The concluding paragraph's statement that 'KVM currently only supports EL0 and EL1 for the guest' should specify that this refers to KVM/ARM and should clarify that EL2 and EL3 execution is unsupported for the guest, which is consistent with the paper's stated scope but should be worded precisely.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: this is a measurement study; the speedup claims are empirically measured against an ISS baseline and do not reduce to fitted inputs or self-cited derivations.

full rationale

The paper's central claim is an empirical performance comparison: the proposed ARM-on-ARM KVM-based multicore SystemC-TLM model is benchmarked against the ISS-based A VP64 baseline, and the reported speedups (up to 10x for Dhrystone, more than 100x for some MiBench workloads) are ratios of measured wall-clock times. There is no derivation chain in which an output quantity is defined in terms of an input quantity, no fitted parameter is later renamed as a prediction, and no uniqueness theorem is imported from the authors' prior work to force a modeling choice. Self-citations to prior work by the same authors (refs [3], [16], [17]) provide engineering provenance for the single-core KVM proof of concept and the parallelization technique; they are not used as evidence for the new speedup figures. The benchmark workloads (Dhrystone, Linux boot, STREAM, MiBench, NAS Parallel Benchmarks) are external and independent. The fact that the proposed platform ran on an Apple M2 Pro while the ISS baseline ran on an AMD Ryzen 9 3900X is a potential threat to the validity or fairness of the speedup magnitude, but it is not circularity: the comparison does not reduce to the paper's inputs by construction. No circular step is identified, so the score is 0.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

No free parameters or invented entities appear in this implementation study. The assumptions are standard engineering domain assumptions about KVM, ARM exception levels, Linux idle behavior, and wall-clock-based cycle estimation.

assumptions (4)
  • domain assumption The host and target architectures are both ARM, and the host provides virtualization extensions with Linux KVM support.
    The entire method depends on same-ISA native execution; ARMv8 VHE and KVM are cited in Section II-B.
  • domain assumption The target workload executes only at exception levels EL0 and EL1.
    Section VI states KVM currently only supports EL0 and EL1 guests, so EL2 hypervisors and EL3 trusted firmware cannot be simulated.
  • domain assumption The target software is a Linux OS whose ELF contains the cpu_do_idle symbol with a recognizable WFI instruction for breakpoint-based idle-loop annotation.
    Section IV-C searches for cpu_do_idle and sets a breakpoint on the WFI instruction; the conclusion notes the approach needs adaptation for non-Linux workloads.
  • domain assumption The number of simulated instructions is approximated from wall-clock KVM runtime divided by the vCPU clock frequency, assuming a constant average execution time per instruction.
    Section IV-A states 'a constant average execution time per instruction is assumed', which makes simulated time sensitive to host scheduling and frequency scaling.

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Cite this review

Pith. "Pith review of High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms." pith.science (2026). https://pith.science/paper/TKLONO3T

@misc{pith2026250512987,
  author       = {Pith},
  title        = {Pith review of: High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/TKLONO3T}},
  note         = {Machine review of arXiv:2505.12987}
}
read the original abstract

The increasing complexity of hardware and software requires advanced development and test methodologies for modern systems on chips. This paper presents a novel approach to ARM-on-ARM virtualization within SystemC-based simulators using Linux's KVM to achieve high-performance simulation. By running target software natively on ARM-based hosts with hardware-based virtualization extensions, our method eliminates the need for instruction-set simulators, which significantly improves performance. We present a multicore SystemC-TLM-based CPU model that can be used as a drop-in replacement for an instruction-set simulator. It places no special requirements on the host system, making it compatible with various environments. Benchmark results show that our ARM-on-ARM-based virtual platform achieves up to 10 x speedup over traditional instruction-set-simulator-based models on compute-intensive workloads. Depending on the benchmark, speedups increase to more than 100 x.

Figures

Figures reproduced from arXiv: 2505.12987 by the authors.

Figure 1
Figure 1. vCPU integration using KVM. However, if both architectures match and Virtualization Host Extensions (VHE), such as ARMv8’s VHE [1], are available on the host, the target SW can be executed natively without the need for an ISS [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Multithreaded approach using a SW-based watchdog. [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. vCPU model execution loop. Then, the cause of the KVM_RUN exit is determined. In case of an MMIO access, a TLM transaction is sent to the corresponding peripheral. Since, according to the SystemC standard, interactions with other models need to be performed in the main thread, this access has to be shifted back in case of parallel execution [2], [16]. If the exit was caused by an idling core that executed a WFI inst… view at source ↗
Figures from the paper (4 more)
Figure 4
Figure 4. Figure 4: AoA-based VP. 1) Symbol search: Identify the cpu_do_idle symbol within the target-SW ELF file. 2) Breakpoint setting: Locate the WFI instruction inside this function and set a breakpoint on it. 3) Instruction check: When a vCPU reaches this breakpoint, KVM exits back t…
Figure 5
Figure 5. Figure 5: Bare-metal Dhrystone [19] benchmark. A. Bare-Metal Dhrystone Benchmark The first benchmark executed is a bare-metal Dhrystone [19], which is single threaded and integer based. For multicore sys￾tems, each core executes its own instance of Dhrystone. Thus, a parallel Dh…
Figure 6
Figure 6. Figure 6: a illustrates the wall-clock time required for different core counts without WFI annotations (see Section IV-C, WFI is handled by KVM). While the single-core VP boots Linux in approximately 0.6 s, multicore setups take considerably longer. A non-parallelized boot of an…
Figure 7
Figure 7. Figure 7: Benchmark speedup S of AoA compared to AVP64 for 1 ms quantum and activated parallel execution. instructions is less expensive for ISSs than for AoA due to the needed context switching for exiting KVM [20]. 1) STREAM: The first user space benchmark tested is STREAM [25…

Discussion (0). Continue with ORCID to comment.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Bridging the Gap: Physical PCI Device Integration Into SystemC-TLM Virtual Platforms

    cs.SE 2025-05 conditional novelty 5.0 of 10

    Real PCIe devices can be integrated into SystemC-TLM virtual platforms using VFIO, achieving up to 480x speedups on AI inference workloads.

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