Pith. sign in

REVIEW 1 cited by

Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis

Not yet reviewed by Pith; the record is open.

This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.

SPECIMEN: schema-true, not a live event

T0 review · schema-true

One-sentence machine reading of the paper's core claim.

pith:XXXXXXXX · record.json · timestamp

arxiv 2104.14155 v1 pith:U24PDHGP submitted 2021-04-29 cs.AR

Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis

classification cs.AR
keywords applicationcgraprocessingspecializedarchitecturearchitecturesautomateddomain
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
0 comments
read the original abstract

The architecture of a coarse-grained reconfigurable array (CGRA) processing element (PE) has a significant effect on the performance and energy efficiency of an application running on the CGRA. This paper presents an automated approach for generating specialized PE architectures for an application or an application domain. Frequent subgraphs mined from a set of applications are merged to form a PE architecture specialized to that application domain. For the image processing and machine learning domains, we generate specialized PEs that are up to 10.5x more energy efficient and consume 9.1x less area than a baseline PE.

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays

    cs.AR 2026-05 conditional novelty 6.0

    DICE achieves 1.77-1.90x dynamic energy efficiency and 42-46% power reduction versus modeled NVIDIA Turing SMs by executing SIMT workloads on pipelined CGRAs with p-graphs handling dynamism and 68% fewer register file...