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High-Bandwidth, Low-Computational Approach: Estimator-Based Control for Hybrid Flying Capacitor Multilevel Converters Using Multi-Cost Gradient Descent and State Feedforward

T0 review · 5 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read This paper tries to establish that a hybrid estimator—closed-loop gradient descent plus open-loop state feedforward—can replace isolated flying-capacitor voltage sensors in hybrid FCML converters, achieving high-bandwidth active voltage…

desk verdict A solid hybrid estimator for FCML with honest feasibility analysis; the no-sensor high-bandwidth claim awaits hardware or switched-model validation. read the letter →

arxiv 2411.14707 v1 pith:U43ALAFD submitted 2024-11-22 eess.SY cs.SY

Inhwi Hwang This is my paper · ORCID
classification eess.SYcs.SY
keywords flyingcapacitormultilevelconverterestimator-basedcontrolactivevoltagebalancingstatefeedforwardmulti-costgradientdescentdisjointsamplingAC-DCbucksensorless
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that flying-capacitor voltages in hybrid multilevel converters can be estimated accurately without isolated voltage sensors by combining two updates each sampling period: a closed-loop gradient-descent correction based on pole-voltage samples, and an open-loop feedforward term that integrates the averaged capacitor dynamics using measured inductor current and the previous duty-difference reference. The result would matter because it removes the cost and complexity of isolated sensors and high-frequency sampling, opening FCML converters to low-cost digital controllers in data-center and electric-aircraft power delivery. The authors prove stability and gain bounds, characterize when full-rank observability is achievable, and support the claim with a 6-level AC-DC buck simulation where switch stress stays below 100 V. The strongest ideal-case statement is that with an exact model, the feedforward path makes the estimated voltage equal the actual voltage with no estimation delay.

What carries the argument

The load-bearing object is the hybrid estimator update law of equations (41)–(43): $\hat{v}_c[n] = (I-\alpha\Delta S[n]\Delta S[n]^T)\hat{v}_c[n-1] + \alpha(S_{N-1}v_{in}-v_{sw}[n])\Delta S[n] + \tau_s i_L[n]\Delta d^*[n-1]/C_f$. The first two terms are a gradient-descent projection of the estimation error onto the switching-state vector $\Delta S$, a rank-one update at each instant; the last term is an open-loop prediction built from the averaged plant dynamics $C_f\,d\langle v_c\rangle/dt = \langle i_L\rangle\Delta d$. The argument reduces to linear algebra about the rank-one matrix $\Delta S\Delta S^T$: its eigenvalues are $0$ and $\Delta S^T\Delta S$, so the feedback loop is stable when $0<\alpha\Delta S^T\Delta S<2$, and full observability over a sampling cycle requires the union of sampled $\Delta S$ vectors to span $\mathbb{R}^{N-2}$. Disjoint sampling at the peaks and valleys of the phase-shifted PWM carriers supplies those vectors.

What would settle it

Run a 6-level AC-DC buck hardware prototype at about 25 kHz sampling with the proposed estimator, deliberately detune $C_f$ by $\pm20\%$, and compare the estimated capacitor voltages against an isolated reference sensor; the claim fails if the 120 Hz estimation error exceeds the bound predicted by equation (72) or if switch stress reaches 100 V with feedforward enabled. A second test is a frequency-response measurement from $v_c$ to $\hat{v}_c$, checking whether the feedforward path actually removes the estimation delay shown in the Bode plots of Fig. 13.

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Extended reading notes

Core claim

The paper's central claim is that the flying-capacitor voltage vector $v_c$ can be reconstructed from pole-voltage samples and measured inductor current by combining two updates each sampling period: a feedback term that runs a multi-cost gradient descent with update matrix $I-\alpha\Delta S[n]\Delta S[n]^T$, and a feedforward term $\tau_s i_L[n]\Delta d^*[n-1]/C_f$ that integrates the averaged plant model. The authors prove that the feedback system matrix has eigenvalues $\{1,\;1-\alpha\Delta S^T\Delta S\}$, giving a stability interval $0<\alpha<2/(N-2)$, and they bound the high-frequency and DC estimation errors that arise from the rank-one nature of each instantaneous update. They argue that in the ideal case the feedforward path makes $\hat{v}_c/v_c\approx 1$ with zero estimation delay, and they identify the operating conditions—$N=3$, $N=4$, and $N=6$ with $|\Delta d|\le 0.2$—under which disjoint PWM-carrier sampling yields full-rank observability.

Load-bearing premise

The feedforward predictor assumes the averaged model $C_f\,d\langle v_c\rangle/dt = \langle i_L\rangle\Delta d$ is exact over each sampling interval, so the sampled inductor current and the previous duty-difference reference fully determine the capacitor-voltage change, with no unmodeled deadtime, measurement delay, or parasitic effects, and with duty differences inside the full-rank region.

Editorial extensions

If this is right

  • A single MCU CPU sampling at about 25 kHz can run estimator-based current control and active balancing for a 6-level FCML converter, eliminating isolated voltage sensors and their hardware cost.
  • The eigenvalue bound $\alpha<2/(N-2)$ combined with the upper and lower gain formulas (62) and (73) gives an implementable tuning procedure for the estimator.
  • Full-rank operation is guaranteed for $N=3$ and $N=4$, and for $N=6$ when active-balancing duty differences are constrained by $|\Delta d|\le 0.2$; $N=5$ and $N\ge7$ require additional sensors to relax the observability condition.
  • Because the feedback path acts as a low-pass filter and the feedforward path as a high-pass filter, the hybrid estimator keeps bandwidth high without requiring the sampling rate of a feedback-only approach.
  • In the 6-level AC-DC buck simulation, the hybrid estimator keeps switch stress below 100 V, while disabling feedforward raises stress to nearly 200 V, showing the feedforward term is load-bearing for the claimed performance.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If verified on hardware, the same estimator structure likely extends to other multilevel topologies whose averaged capacitor dynamics factor as current times a duty-difference vector, since the stability proof uses only the rank-one update structure.
  • The paper's gain bounds suggest an adaptive choice of $\alpha$ could trade high-frequency sampling noise against DC offset error online; the necessary formulas are given, but adaptation is not explored.
  • The $N=5$ full-rank failure, caused by peak-valley overlap of the PSPWM carriers, could potentially be cured by alternative sampling patterns or carrier phase shifts, a testable modification of the algorithm in Fig. 16.
  • The ideal-case exactness of the feedforward term points directly to model-error sensitivity, so a natural next experiment is to deliberately detune $C_f$ and deadtime compensation and measure how quickly estimation error approaches the bound in equation (72).
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 5 minor

Summary. The paper proposes a hybrid estimator for flying-capacitor voltages in an N-level FCML converter, combining a closed-loop gradient-descent update based on pole-voltage samples with an open-loop feedforward term based on the sampled inductor current and the previous duty-difference reference. The authors provide a discrete-time eigenvalue stability analysis, a gain-setting procedure with upper and lower bounds, a numerical feasibility study of full-rank disjoint sampling, and a simulation of a 6-level AC-DC buck converter in which the estimator keeps switch stress below 100 V until the feedforward is disabled. The central claim is that the feedforward path makes the estimated capacitor voltages track the actual values with no estimation delay, enabling high-bandwidth active voltage balancing and current control without isolated voltage sensors.

Significance. If the claims are substantiated, the paper would offer a useful practical contribution: a capacitor-voltage estimation scheme for FCML converters that avoids isolated sensors and reduces sampling/control frequency, with explicit stability and gain-guidance. The strengths are the eigenvalue-based stability condition (Eqs. 44-48), the identification of the rank-deficiency limitation across FCML levels and duty-ratio constraints (Section III-H, Table II), and the simulation comparison with and without feedforward (Fig. 18). However, the central performance claim rests on the feedforward path being an exact model of the plant, and the frequency-response analysis is not rigorous for a time-varying estimator. The lack of experimental or switched-model validation under non-ideal effects (deadtime, sampling mismatch, parasitics) leaves the high-bandwidth, no-sensor claim partially unsupported. The analysis is a reasonable starting point for a journal version but needs substantial strengthening.

major comments (5)
  1. [III-F, Eqs. (49)-(56), Figs. 12-13] The claim that the hybrid estimator tracks the actual capacitor voltage exactly, with no delay (Eqs. 57-58), is an idealization that is not demonstrated under the paper's own implementation assumptions. The feedforward update (40) uses the instantaneous sampled current iL[n] and the previous duty reference Δd*[n-1], while the equality (57) requires the period-averaged current and the actual applied duty. The paper mentions deadtime only in passing near Eq. (40) and provides no deadtime model or compensation. Because the feedback loop at fs=25.53 kHz has low bandwidth (Fig. 12), any feedforward error propagates directly into the capacitor-voltage estimate and hence into switch stress, which is the failure mode the paper uses to motivate the feedforward. The simulation does not report deadtime, sampling-delay, or parasitic effects, so the ideal-case equality is an unverified assumption rather than a demonstrated property. Please add a deadtime/sampling-error sensitivity analysis and a switched-model validation with deadtime and gate delays, or clearly bound the feedforward error and its effect on the tracking guarantee.
  2. [§III-G3, Eq. (73)] The frequency-response analysis treats a time-varying estimator as an LTI system. The feedback gain Kest[n] in Eq. (50) varies at every sampling instant, and Eq. (51) is an approximation that is only valid if the sampling frequency is far above the estimator bandwidth—which is exactly the regime the paper wants to avoid (fs=25 kHz). The quantity Kest,eff(s) in Eq. (53) is defined as a quotient of convolutions that is not a transfer function (and is indeterminate when the error is zero). Consequently, the Bode plots in Figs. 11-13 do not constitute a rigorous demonstration of bandwidth or phase margin. I recommend replacing the LTI Bode analysis with a linear periodically time-varying (LPTV) analysis or explicitly labeling the Bode plots as an approximate design aid and stating the conditions under which the approximation is valid.
  3. [§III-H, Table II] The lower bound on α in Eq. (73) is not an explicit bound: βmax is itself a function of α (Fig. 14), and the expression α ≥ β^{-1}_max(...) is an implicit condition, not a closed-form gain-setting rule. The paper does not provide an algorithm or a formula to evaluate this bound for a given operating point; Fig. 14 is given for a single duty set and N=6. Furthermore, the bound depends on the unknown feedforward error ∥Δṽff∥∞, so the practical guidance is incomplete. Please provide a concrete procedure to compute α from the system parameters and allowable errors, or state explicitly that the bound requires an a priori estimate of the feedforward error and describe how to obtain it.
  4. [IV, Fig. 18] The full-rank feasibility results in Table II are presented as definitive, but they are based on a MATLAB search ('iteratively verified') rather than a mathematical proof. The paper does not specify the resolution of the duty-cycle grid, whether the search covers continuous duty values, or how the result for N=6 with |Δd|≤0.2 is affected by the exact bound. Given that the entire applicability claim of the method to N=6 (and the resulting data-center conclusion) depends on this table, the numerical search needs a precise statement of its grid and, ideally, an analytic proof or counterexample. Also, the text in Section III-H2 says |Δd| is typically limited to 0.05, but Table II and the simulation use Δdmax=0.2; this discrepancy should be resolved.
  5. [V, Conclusion] The simulation results are the only validation of the method, and the manuscript does not state whether the simulation is a switched-model with parasitic elements, deadtime, and sampling quantization, or an averaged model. The voltage-stress waveform in Fig. 18 suggests a switched model, but no deadtime or non-ideal sampling is reported. Since the central claim is about practical low-cost MCU implementation, a detailed description of the simulation setup (including the converter model, sampling instant alignment, PWM deadtime, and gate delays) is necessary to support the conclusions.
minor comments (5)
  1. [Throughout] There are many typographical errors and inconsistent notations, e.g., 'estimatior' in the Index Terms, 'disjoing' in Fig. 6, 'multi-inpue multi-output' in Section II, 'simpicity' in Section III-G3, and Table III uses both Cd and Cf for the flying capacitor. A careful proofreading pass would improve readability.
  2. [Eq. (73) and surrounding text] The notation β^{-1}_max is ambiguous: it could mean the reciprocal or the inverse function. The text says 'decreasing function as shown in Fig. 14,' which suggests the inverse function, but the equation could be misread as a reciprocal. Please clarify.
  3. [Section II-B, Eq. (5)] The symbol ms is used for the sampling divider, but the condition (30) introduces Ns. The mapping between ms and Ns in (31) should be stated more clearly, especially for even vs. odd N, to avoid confusion with the number of sampling instants Ndis.
  4. [Section III-G1, Eq. (62)] The upper bound in (62) depends on max(dvin/dt), which is not a design parameter and may be difficult to estimate in practice. Please discuss how this quantity is determined from the application (e.g., grid frequency and voltage magnitude).
  5. [References] Reference [20] lists page numbers '4291-4411' for a 2020 Transactions paper, which appear implausibly long; please verify the page range. Also, reference [27] is duplicative of [15] (same authors and title) and should be consolidated.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the hybrid estimator is a standard model-based observer whose feedforward path uses the plant model, not a fitted or self-referential prediction.

full rationale

The paper's derivation chain is self-contained and does not reduce to its own inputs. The feedforward term in Eq. (43), Δv̂_ff[n] = τ_s i_L[n] Δd*[n−1]/C_f, is exactly the discretized form of the averaged plant model in Eq. (16), C_f d⟨v_c⟩/dt = ⟨i_L⟩Δd. That is the normal construction of a model-based open-loop predictor, not a circular step: the plant model is an assumed physical dynamic, and the estimator integrates it to predict capacitor-voltage changes. The ideal-case claim in Eqs. (57)–(58), v̂_c/v_c ≈ 1, follows explicitly from substituting that plant model into the feedforward term under zero-parameter-error and ideal-sampling assumptions, which the paper states; it is not a fitted quantity being renamed as a prediction. The feedback update in Eq. (42) is derived from the pole-voltage relation Eq. (38), and the stability analysis (Eqs. (44)–(48)) and gain bounds (Eqs. (61)–(73)) are derived from the system-matrix eigenvalues with stated assumptions. The simulation in Section IV is an independent, nonlinear switched-model validation using the stated parameters in Table III, with the feedforward disabled after t = 0.145 s to demonstrate its role. The paper's self-citations ([22], [23], [31]) are background references or an optional mitigation technique (SAPWM), not load-bearing support for the central estimator derivation. Concerns about deadtime, instantaneous-versus-averaged current sampling, and pole-voltage settling are robustness or assumption-validity issues, not circularity. The derivation chain therefore shows no self-definitional, fitted-input, or self-citation-forced circularity.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The estimator's feedforward path is the integral of the plant model; the feedback path's convergence depends on the full-rank condition, which holds only for limited converter levels. The only free parameters are the feedback gain and the duty-difference limit, both of which are design choices, not fitted values.

free parameters (3)
  • feedback gain alpha = 0.047 (simulation)
    Feedback gain (learning rate) in the multi-cost gradient descent. The upper bound (62) and lower bound (73) restrict alpha, but the simulation picks 0.047 as a design choice within those bounds; it is not fitted to reproduce the output.
  • duty difference limit Delta_d_max = 0.2 (Table II, N=6)
    Maximum duty difference allowed by the active balancing controller (Eq. 18). This is also the limit under which full-rank observability holds for N=6; it is a design constraint rather than a fitted value, but the applicability claim depends on it.
  • sampling divider ms / Ns = 47 (simulation)
    Integer controlling the disjoint sampling pattern. It must satisfy gcd(Ns, 2(N-1)) = 1 for even N (Eq. 30); the value 47 is chosen to satisfy this and set the sampling frequency to 25.53 kHz.
assumptions (4)
  • domain assumption The averaged plant model C_f d<v_c>/dt = <i_L> Δd (Eq. 16) accurately captures the flying capacitor voltage dynamics over each sampling period, and the sampled inductor current and previous duty reference fully determine the capacitor voltage change.
    Used for the feedforward estimator in Eq. (43) and for the active balancing plant in Eq. (16); ignores deadtime, parasitic inductance, and unbalanced capacitor tolerances.
  • domain assumption The pole voltage satisfies v_sw = -ΔS^T v_c + S_{N-1} v_in (Eq. 38) at each sampling instant, meaning the voltage has settled and the switches are ideal.
    This is the measurement model for the feedback estimator; Section III-H acknowledges that near duty cycles d_dead the pole voltage is unsettled, which is exactly a violation of this assumption.
  • domain assumption The span condition (36) holds for the switching state vectors collected over Ndis disjoint sampling instants, i.e., the system is observable over a full sampling cycle.
    The full-rank check in Section III-H, Table II shows this is only true for N=3, N=4, and N=6 with |Δd| ≤ 0.2; the stability proof of Pfr in Section III-G.2 relies on this.
  • standard math The standard spectral properties of the symmetric rank-one update P[n] = I - α ΔS[n]ΔS[n]^T: simultaneous diagonalizability and eigenvalues {1-α||ΔS||^2, 1}.
    Used in Section III-E to derive the stability bound and in Section III-G.2 to analyze the product matrix Pfr.

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Cite this review

Pith. "Pith review of High-Bandwidth, Low-Computational Approach: Estimator-Based Control for Hybrid Flying Capacitor Multilevel Converters Using Multi-Cost Gradient Descent and State Feedforward." pith.science (2026). https://pith.science/paper/U43ALAFD

@misc{pith2026241114707,
  author       = {Pith},
  title        = {Pith review of: High-Bandwidth, Low-Computational Approach: Estimator-Based Control for Hybrid Flying Capacitor Multilevel Converters Using Multi-Cost Gradient Descent and State Feedforward},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/U43ALAFD}},
  note         = {Machine review of arXiv:2411.14707}
}
read the original abstract

This paper presents an estimator-based control framework for hybrid flying capacitor multilevel (FCML) converters, achieving high-bandwidth control and reduced computational complexity. Utilizing a hybrid estimation method that combines closed-loop and open-loop dynamics, the proposed approach enables accurate and fast flying capacitor voltage estimation without relying on isolated voltage sensors or high-cost computing hardware. The methodology employs multi-cost gradient descent and state feedforward algorithms, enhancing estimation performance while maintaining low computational overhead. A detailed analysis of stability, gain setting, and rank-deficiency issues is provided, ensuring robust operation across diverse converter levels and duty cycle conditions. Simulation results validate the effectiveness of the proposed estimator in achieving active voltage balancing and current control with 6-level AC-DC buck FCML, contributing to cost-effective solutions for FCML applications, such as data centers and electric aircraft.

Figures

Figures reproduced from arXiv: 2411.14707 by the authors.

Figure 1
Figure 1. Single swiching cell of flying capacitor converter with adjacent flying capacitors and k-th switch pair. vc,k is the voltage of k-th flying capacitor voltage. Sk and S¯k are the switching states of k-th upper switch and lower switch, respectively. under high-radiation conditions encountered in space [10]. For electric aircraft, FCML’s high power density supports lightweight designs and efficient space utilization, e… view at source ↗
Figure 3
Figure 3. This setup allows each control layer to be designed [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
Figure 2
Figure 2. Circuit diagram of grid-connected buck-type hybrid FCML converter with input filter. vgrid, vin, iL, and vout are grid voltage, input capacitor voltage, inductor current, and output capacitor voltage, respectively [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figures from the paper (15 more)
Figure 3
Figure 3. Figure 3: Block diagram of the estimator-based controller for hybrid FCML converter. vsw represents the pole voltage, while ˆvc denotes the estimated flying capacitor voltage. ∆d∗ is the output of the voltage balancing controller, d ∗ is the duty cycle reference, and i ∗ L refer…
Figure 4
Figure 4. Figure 4: Block diagram of generalized proportional-integral-resonant (PIR) controller. x is the target variable under control and y is the output variable for controlling x. γ is the variable to enable and disable some parts of the generalized PIR controller. F(s) is the transf…
Figure 5
Figure 5. Figure 5: The figure of PSPWM carriers when N = 5 and N = 4. When N is an odd number, the peak of one PWM carrier coincides with the valley of another. Conversely, when N is an even number, no such overlap occurs, as the peaks and valleys are evenly distributed across the carrie…
Figure 6
Figure 6. Figure 6: Disjoing sampling with ms = 7 for 6-level FCML converter with 5 PSPWM carriers where Ndis = 10. Disjoint sampling ensures that all sampling points coincide with all the peaks and valleys of the PSPWM carriers. To determine whether a sampling point corresponds to a peak…
Figure 7
Figure 7. Figure 7: A graph showing the original cost function of convex optimization and multi-cost functions. The figure illustrates an example of convex optimization with two variables. Multi-cost matrices are all single rank. The optimal solution of the original cost function is shown…
Figure 8
Figure 8. Figure 8: Block diagram of hybrid flying capacitor voltage estimator. * * * Stable Unstable * * [PITH_FULL_IMAGE:figures/full_fig_p009_8.png]
Figure 9
Figure 9. Figure 9: A figure illustrating closed-loop estimation of flying capacitor voltage where vc,i, vc,j , vc,k is the component of vc with non-zero ∆Si[n], ∆Sj [n], and ∆Sk[n]. The update vector (ˆvc[n] - ˆvc[n−1]) for the next prediction is the projection of the error vector (vc[n]…
Figure 10
Figure 10. Figure 10: Real-time estimation simulation result using a feedback-only estimator. As N increases, the bandwidth decreases sharply, leading to higher high-frequency errors and increased estimation errors at 120 Hz. A larger α results in a higher average bandwidth, reducing the 1…
Figure 11
Figure 11. Figure 11: Bode plots of diagonal transfer functions for closed￾loop estimator, where fs = 25 kHz, α = 0.02, and d = [0.42, 0.37, 0.41, 0.46, 0.5]T. Even if the bandwidth of diagonal transfer function has high-bandwidth, non-diagonal term makes the effective bandwidth much lower…
Figure 12
Figure 12. Figure 12: Bode plots of transfer functions for closed-loop estimator considering maximum eigenvalue of Pfr, where fs = 25 kHz and d = [0.42, 0.37, 0.41, 0.46, 0.5]T. Compared to bode plot of diagonal transfer function in [PITH_FULL_IMAGE:figures/full_fig_p011_12.png]
Figure 13
Figure 13. Figure 13: Bode plot of the hybrid estimator considering maximum eigenvalue of Pfr, where fs = 25 kHz and d = [0.42, 0.37, 0.41, 0.46, 0.5]T. Compared to the feedback estimator shown in [PITH_FULL_IMAGE:figures/full_fig_p012_13.png]
Figure 14
Figure 14. Figure 14: Graph showing the variation of βmax and Ndis/(1 − βmax) as functions of α, where N = 6, fs = 25 kHz, and d = [0.42, 0.37, 0.41, 0.46, 0.5]T. As α increases, the α-dependent βmax decreases, leading to a reduction in Ndis/(1 − βmax), which affects the DC offset error. C…
Figure 16
Figure 16. Figure 16: Algorithm to verify the feasibility of full-rank operation. The algorithm checks whether the disjoint sampling ∆S satisfies the full-rank condition across all duty cycle regions. When constraints are imposed on ∆d due to active balancing, the algorithm evaluates full-…
Figure 17
Figure 17. Figure 17: Block diagram of the utilized control system for estimator-based control [PITH_FULL_IMAGE:figures/full_fig_p016_17.png]
Figure 18
Figure 18. Figure 18: Results of estimator-based output capacitor voltage / active balancing / current control using the proposed hybrid estimator. the proposed estimator by demonstrating DC current control for output voltage regulation under a varying input voltage of 120 Hz. The sampling…

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Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.