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REVIEW 4 major objections 7 minor 45 references

This paper claims that grouping statistically correlated cache blocks onto the same racetrack-memory nanowire, and picking victims based on where those correlated blocks live in neighboring cache sets, cuts shift operations by 49.0% and cac

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2026-08-01 18:29 UTC pith:U57LDD65

load-bearing objection ISCA is a genuinely new vertical-DBC placement plus correlation-aware replacement scheme with solid simulated numbers, but the 49% shift reduction isn't cleanly attributed—the design changes both layout and victim selection at once and no artifacts are released. the 4 major comments →

arxiv 2607.17274 v1 pith:U57LDD65 submitted 2026-07-19 cs.AR cs.ET

Inter-Set Correlation-Aware Replacement Policy for Energy Efficient RTM-based Caches

Elham Cheshmikhani , Hamed Farbeh This is my paper
classification cs.AR cs.ET
keywords racetrack memorycache replacement policyshift overheadinter-set correlationenergy efficiencylast-level cachevertical domain block clusternon-volatile memory
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Racetrack memory stores many bits on a nanowire and reads them serially at a port, so every access costs shifts that move data along the wire; in a conventional cache, those shifts serve only the one requested block and do not help the blocks that will be requested next. The paper establishes that the blocks actually requested close in time are usually adjacent blocks in memory, which land in adjacent cache sets and share the same tag. It reorganizes the cache so each nanowire holds blocks from several consecutive sets (a vertical domain-block cluster) and introduces a replacement policy, ISCA, that on a miss searches neighboring sets for a block with the same tag and places the incoming block in that same way, so one shift simultaneously brings the next likely request closer to the port. Simulations with SPEC CPU2017 show this reduces shifts per access by 49.0% and cache energy by 35.9% at a 1.1% IPC cost, and the benefit holds when nanowires are lengthened fourfold to cut area by 43.1%.

Core claim

In a conventional RTM last-level cache, a set of k ways is built from a horizontal domain block cluster (DBC): one nanowire holds one bit from each way, so shifting to read one block also shifts all other ways in that set, but those ways contain unrelated blocks that are not likely to be accessed next. The paper first measures that 84.5% of accesses find a block with a similar tag in an adjacent cache set, and nearly half of consecutive accesses go to adjacent sets. It then proposes a vertical DBC where each nanowire instead holds one way from k consecutive sets, so a single shift moves blocks from multiple sets at once. The rate of shifts stays high (5.4 per access, the same as the baseline

What carries the argument

The central object is the vertical Domain Block Cluster (DBC): a nanowire track that holds the same way position across a contiguous block of cache sets (a superset), instead of holding all ways of one set as in the conventional horizontal DBC. The paper's insight is that because consecutive memory blocks share a tag and map to adjacent sets, a vertical DBC lets a single shift motion reproduce the inter-set access order. The load-bearing mechanism is the ISCA replacement policy, which performs tag comparisons in the upper and lower adjacent sets on a cache miss and selects a victim in the way where a same-tag correlated block is found, thereby placing the incoming block on the same track as

Load-bearing premise

The whole benefit rests on the premise that the inter-set access locality measured in the conventional horizontal DBC—where a block in an adjacent set with the same tag is both resident at miss time and a reliable predictor of the next access—still holds when the cache is reorganized into vertical DBCs and runs a wide range of real workloads.

What would settle it

Run ISCA on a multicore system with the same gem5 setup but with the LLC set-index bits XOR-masked or hashed, and compare shifts per access and IPC against the contiguous-index case; if the 49.0% shift reduction collapses to the level of distance-only victim selection (roughly the SAR baseline) or IPC degrades beyond a few percent, the correlation signal is an artifact of the baseline index mapping rather than a general property of the workloads.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • If the shift reduction holds, RTM's main architectural drawback—serialized access—becomes manageable enough for RTM to serve as a last-level cache rather than only a storage-class memory.
  • Track length no longer needs to equal cache associativity; the paper shows 64-bit tracks yield only a 1.4x shift increase over 16-bit tracks while cutting access-transistor count by 4x, so higher-density caches become feasible.
  • Because ISCA keeps no history table and only adds tag comparisons in adjacent sets on misses (hidden behind the miss fetch), the scheme is cheap to integrate on top of existing replacement policies such as LRU, RRIP, or SHiP.
  • The paper's 49.0% shift reduction and 35.9% energy reduction should translate to proportionally lower access latency and static power in a real RTM LLC, making energy-constrained server and edge processors the most direct beneficiaries.
  • The correlation signal (same tag in adjacent sets) indicates that workloads with strong spatial locality and contiguous set-index mapping will gain the most, while the scheme degrades gracefully to nearest-port victim selection for workloads lacking that signal.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • A testable extension is to hash or randomly permute the set-index bits: the paper's entire correlation search relies on adjacent sets holding adjacent memory blocks, so ISCA's 49.0% shift reduction should largely vanish under index randomization—measuring that drop would cleanly separate the correlation mechanism from other side effects of the vertical DBC.
  • The correlation detector could be strengthened beyond tag equality, for example by recording the order of accesses across sets and placing blocks in track positions according to that observed order; the paper places correlated blocks on the same track but does not sort their positions along the track to match access sequence, so a position-ordered variant might cut shifts further.
  • Because the vertical DBC decouples track length from associativity, it opens a dynamic control knob—superset size—that the paper does not explore; adapting superset size to the workload's inter-set distance could extend the energy benefit to mixed or phase-changing workloads.
  • The scheme's reliance on contiguous set indexing suggests it would interact poorly with cache-decoupling or skewed-associative designs, which intentionally break the index-to-address correspondence; in such designs ISCA would need a remapping step to retain its correlation signal.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

4 major / 7 minor

Summary. The paper analyzes conventional RTM-based last-level caches, where each cache set is implemented by a horizontal Domain Block Cluster (DBC) and all ways in a set share the access port. The authors observe that a single shift operation places only one block at the port and does not benefit subsequently accessed blocks, resulting in redundant shifts. They measure intra-set and inter-set access distances and tag similarities in SPEC CPU2017 workloads, finding that adjacent cache sets frequently contain blocks with similar tags and that consecutive accesses often target adjacent sets. Based on this, they propose a vertical DBC organization in which consecutive sets share a DBC per way, and an Inter-Set Correlation Aware (ISCA) replacement policy. On a cache miss, ISCA searches the upper set first, then the lower set, for a block with a similar tag; if found, the incoming block is placed in the same way, otherwise a victim near the access port is chosen among the older half of the set's blocks. Using gem5 with DESTINY-extracted RTM parameters and 33 SPEC CPU2017 workload mixes, the paper reports a 49.0% reduction in shift overhead, 35.9% reduction in cache energy, and 1.1% IPC degradation compared to TapeCache, with further scaling results for 64-bit tracks.

Significance. If the causal attribution is correct, this is a useful contribution: the vertical DBC layout and ISCA policy require no metadata storage or history table, and they exploit spatial locality to make each shift also serve subsequent accesses. The paper provides a clear motivation with measured inter-set locality, a concrete structure, and a standard gem5/DESTINY evaluation across 33 multi-programmed workloads with comparisons to TapeCache, V-TapeCache, SAR, and BlendCache. The claimed improvements are substantial and, for the single configuration evaluated, are internally consistent with the described simulation. However, the absence of code, simulator configurations, and run-to-run variance, together with the lack of a control arm separating the correlation search from the vertical layout and distance-based victim selection, means the central causal claim is not yet fully supported.

major comments (4)
  1. [§III-C and §IV-B, Figs. 12–13] The paper attributes the 49.0% SPA reduction to inter-set correlation placement, but the comparison matrix does not isolate the correlation-search mechanism. ISCA differs from V-TapeCache (vertical LRU) in both layout and victim selection, and from SAR (horizontal shift-aware) in layout; there is no vertical-DBC baseline with distance-aware victim selection but without adjacent-set tag search. Fig. 13 itself reports that only 18.6% of misses find a correlated block, while 26.8% find a nearest-port victim and the remainder require ≥2 shifts. With over 80% of victim selections not driven by tag similarity, a vertical-DBC-plus-nearest-port-without-correlation-search ablation is necessary to know how much of the 49.0% gain is due to the novel search mechanism rather than to the vertical layout and shift-aware selection. Without this arm, the central claim is not established.
  2. [§IV-A and §III-C] The policy depends on several hand-set parameters: the 50% LRU age threshold (IV-A), the upper-set-first search order (III-C), and the track/superset length of 16 (IV-A, IV-C). These choices are motivated by the same SPEC CPU2017 measurements used in the evaluation, and no sensitivity analysis is provided. For example, the paper does not report behavior with threshold 25% or 75%, with lower-set-first search, or with track lengths other than 16 and 64. Since the scheme's benefit relies on adjacent-set same-tag locality, a sensitivity study varying these parameters is needed to show the results are not artifacts of the chosen operating point.
  3. [§IV-A and absence of artifacts] The evaluation is entirely simulation-based, but no simulator version, cache configuration details, DESTINY modification, or workload mix compositions are released. The workload labels (Mix_0 to Mix_32) do not list the member benchmarks, and there are no standard deviations or run-to-run variance values. This makes the numerical claims (49.0%, 35.9%, 1.1%) impossible to reproduce or verify. For a paper whose conclusions rest on simulation numbers, this is a serious reproducibility concern that should be addressed before publication.
  4. [§III-A vs. §IV] The design choices are derived from the same SPEC CPU2017 traces used for evaluation: the upper-set-first search order is chosen from the measured 41.5%/6.1% same-tag probabilities, and the adjacent-set locality is the central motivating observation. This is not an internal inconsistency, but it is a circularity risk for generalization. The paper should validate on held-out workloads, or at least on a different benchmark suite and with an address-hashing scheme that breaks adjacent-set correlation (e.g., bit-reversal or randomized set index), to confirm that the mechanism, not the specific mapping of the SPEC binaries, is what drives the energy savings.
minor comments (7)
  1. [§III-C] The text states the lower-set same-tag probability is 6.9%, but Fig. 3 and §III-A report 6.1%. Please correct the inconsistency.
  2. [Fig. 13] The figure appears to show only two categories (Similar Tag and Minimum Distance), while the text describes a third outcome (other victims requiring ≥2 shifts). The remainder should be shown explicitly or clarified in the caption so that the reader can see the distribution sums to 100%.
  3. [§III-A] The text refers to 'Section 5 (Table I)' for the system configuration, but the configuration is described in Section IV-A. The cross-reference should be corrected.
  4. [Table I] The row '2-cycle shift latency' should clarify whether this is the latency per one-position shift or per access, and how it interacts with the reported distances in bits.
  5. [§IV-C] The statement that MPKI and the probability of finding correlated blocks 'are not meaningfully affected' by track length is unsupported because those data are 'not reported.' Please either provide the numbers or explain the basis for this claim.
  6. [§IV-D] The hardware-complexity argument that finding a nearest-port victim is 'similar to finding a block with maximum age in LRU' is qualitative. A quantitative estimate of the added comparators, muxing, or critical-path delay would substantiate the claimed negligible overhead.
  7. [General] Fig. 19 contains a typo ('BlecdCache-16'), and there is a minor spelling inconsistency ('BlendeCache' vs. 'BlendCache') in the related-work section and Fig. 12 captions.

Circularity Check

0 steps flagged

No significant circularity; the central claims are measured simulation results against external baselines, not derived from their inputs.

full rationale

The paper's chain is observational motivation -> proposed placement/replacement heuristic -> full-system simulation. Section III-A establishes that adjacent cache sets frequently contain same-tag blocks and that consecutive accesses land in nearby sets. This motivates the vertical DBC placement and ISCA victim search, but the 49.0% SPA and 35.9% energy numbers in Section IV-B are outcomes of gem5 simulations with SPEC CPU2017 (external benchmarks), not algebraic consequences of the measured tag-similarity probabilities. The search order ('upper set first') and 50% LRU threshold are design decisions, not fitted parameters that are then renamed as predictions; no equation in the paper reduces to its own input. The paper's self-citations ([10], [9], etc.) are background references for RTM/NVM technology and are not load-bearing for the main claim. The skeptic's concern that the correlation search is only active on 18.6% of misses and that nearest-port selection may drive part of the gain is a legitimate experimental-attribution limitation, but it is not definitional or self-referential circularity under the criteria here. Hence the appropriate finding is no significant circularity.

Axiom & Free-Parameter Ledger

3 free parameters · 4 axioms · 0 invented entities

No new physical entities are introduced; vertical DBC is an architectural reorganization of existing RTM structures. The main tunable knobs are the LRU age threshold, the upper-set-first search order, and track length. The core load-bearing assumptions are spatial-locality persistence and the accuracy of the DESTINY/gem5 energy and timing models.

free parameters (3)
  • LRU age threshold (50%) = 50% (upper half of older blocks)
    ISCA restricts victim candidates to the older half of a set when combined with LRU. The threshold is chosen without sensitivity analysis and directly affects how often correlated-block placement succeeds (Sections III-D, IV-A).
  • Upper-set-first search order = Upper set searched before lower set
    Search order is fixed based on the measured upper-set 41.5% versus lower-set 6.1% same-tag probabilities from the same SPEC workloads (Fig. 3), so it is tuned to the evaluation set.
  • Track/superset length = 16-bit; 64-bit in scalability experiments
    Track length is a design choice: 16-bit is used for fair comparison with 16-way associativity, 64-bit for scalability. It determines shift distances and is not swept as a sensitivity variable.
axioms (4)
  • domain assumption Adjacent memory blocks map to adjacent cache sets and are accessed close in time due to spatial locality.
    Underlies the tag-similarity observation in Fig. 3 and the entire vertical-DBC grouping idea (Section III-A).
  • domain assumption Shift operations account for more than 50% of RTM cache energy.
    Cites prior work [25], [27]; used to translate shift reduction into energy savings (Sections I, IV-B).
  • domain assumption The gem5 + modified DESTINY simulation models RTM cache timing and energy accurately for 16-bit and 64-bit tracks.
    No validation against silicon is given; all quantitative claims depend on these models (Section IV-A).
  • domain assumption Cache capacity, associativity, and tag comparison behavior are unchanged by the vertical DBC re-mapping.
    The paper claims area is unchanged and miss-rate effects arise only through replacement policy (Sections III-B, III-D).

pith-pipeline@v1.3.0-alltime-deepseek · 18387 in / 13962 out tokens · 139710 ms · 2026-08-01T18:29:16.091545+00:00 · methodology

0 comments
read the original abstract

Today's data-centric applications demand cache architectures that can scale with growing workloads while maintaining high performance and energy efficiency. Fundamental issues such as excessive area consumption and leakage power are increasingly challenging traditional SRAM-based caches, thereby motivating the exploration of non-volatile alternatives. Among these, racetrack memory (RTM) stands out due to its remarkable storage density, achieved through nanowires hosting sequential magnetic domains that can be manipulated via domain wall or skyrmion techniques. Despite its advantages, racetrack memory's inherent serialized access introduces considerable shift overhead, leading to elevated energy consumption and latency. In this paper, we analyze the placement strategies in conventional RTM-based last-level caches and identify that current methods trigger redundant shift operations as a shift intended to read one block fails to preposition other blocks subsequently accessed. To resolve this, we introduce an innovative data placement and replacement scheme that intelligently groups correlated blocks, ensuring that a single shift not only retrieves the target block but also aligns subsequent blocks closer to the access port. Our simulation results using the gem5 simulator and the SPEC CPU2017 benchmarks reveal that our scheme reduces shift overhead by 49.0% and cache energy consumption by 35.9% with negligible performance impact. In addition, this scheme exhibits robust scalability to longer nanowire tracks for higher cache density.

Figures

Figures reproduced from arXiv: 2607.17274 by Elham Cheshmikhani, Hamed Farbeh.

Figure 1
Figure 1. Figure 1: RTM-cache structure in conventional design, where each cache set (all its ways) is constructed by a DBC consisting [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Intra-set distance in consecutive accesses to LLC sets in various workloads. Intra-set distance value determines the [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Probability of finding a tag in adjacet upper and lower sets (previous and next sets) similar to the tag of requested [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Inter-set distance in consecutive accesses to LLC in various workloads for a) Supersets with 16 sets and b) Supersets [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Set number accessed in consecutive requests to a randomly-selected superset of RTM-cache for a window of 1000 [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Probability of accessing adjacent sets (inter-set distance [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 9
Figure 9. Figure 9: Number of shifts per access in the proposed vertical [PITH_FULL_IMAGE:figures/full_fig_p007_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Visualization of cache block allocation in conventional [PITH_FULL_IMAGE:figures/full_fig_p007_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Control flow of the cache in the proposed replacement [PITH_FULL_IMAGE:figures/full_fig_p008_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Number of shifts for evaluated schemes normalized to TapeCache baseline for various workloads. [PITH_FULL_IMAGE:figures/full_fig_p010_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Probability of finding a similar tag in adjacent sets or [PITH_FULL_IMAGE:figures/full_fig_p010_13.png] view at source ↗
Figure 16
Figure 16. Figure 16: Miss per kilo instructions (MPKI) for evaluated [PITH_FULL_IMAGE:figures/full_fig_p010_16.png] view at source ↗
Figure 19
Figure 19. Figure 19: Instructions per cycle (IPC) considering 64-bit track [PITH_FULL_IMAGE:figures/full_fig_p011_19.png] view at source ↗
Figure 18
Figure 18. Figure 18: Energy consumption considering 64-bit track length [PITH_FULL_IMAGE:figures/full_fig_p011_18.png] view at source ↗

discussion (0)

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Reference graph

Works this paper leans on

45 extracted references · 1 linked inside Pith

  1. [1]

    Nassif, A

    N. Nassif, A. O. Munch, C. L. Molnar, G. Pasdast, S. V . Lyer, Z. Yang, O. Mendoza, M. Huddart, S. Venkataraman, S. Kandulaet al., “Sapphire 0 0.5 1 1.5 2 2.5 3 3.5IPC Workloads TapeCache-16 V-TapeCache-64 BlecdCache-16 ISCA-64 Fig. 19: Instructions per cycle (IPC) considering 64-bit track length (64-set supersets) for evaluated schemes normalized to Tape...

    2022

  2. [2]

    Amd next generation “zen 4

    R. Bhargava and K. Troester, “Amd next generation “zen 4” core and 4th gen amd epyc™ server cpus,”IEEE Micro, 2024

    2024

  3. [3]

    Ibm unveils new generation of ibm power servers for frictionless, scalable hybrid cloud,

    IBM, “Ibm unveils new generation of ibm power servers for frictionless, scalable hybrid cloud,” September 2021, retrieved December 11, 2022 from https://www.ibm.com

    2021

  4. [4]

    An energy-efficient cache re- placement policy for ultra-dense racetrack memory,

    F. Hameed, M. Maqsood, and S. A. Irtaza, “An energy-efficient cache re- placement policy for ultra-dense racetrack memory,”Journal of Systems Architecture, vol. 137, p. 102837, 2023

    2023

  5. [5]

    Roadmap for ferroelectric domain wall memory,

    J. Sun, Y . Li, D. Hu, B. Shen, B. Zhang, Z. Wang, H. Tang, and A. Jiang, “Roadmap for ferroelectric domain wall memory,”Microstructures, vol. 4, no. 1, pp. N–A, 2024

    2024

  6. [6]

    Downshift: Tuning shift reduction with reliability for racetrack memo- ries,

    A. A. Khan, S. Ollivier, F. Hameed, J. Castrillon, and A. K. Jones, “Downshift: Tuning shift reduction with reliability for racetrack memo- ries,”IEEE Transactions on Computers, vol. 72, no. 9, pp. 2585–2599, 2023

    2023

  7. [7]

    Copa: Cold page awakening to overcome retention failures in stt-mram based i/o buffers,

    M. Hadizadeh, E. Cheshmikhani, M. Rahmanpour, O. Mutlu, and H. Asadi, “Copa: Cold page awakening to overcome retention failures in stt-mram based i/o buffers,”IEEE Transactions on Parallel and Distributed Systems, vol. 33, no. 10, pp. 2304–2317, 2021

    2021

  8. [8]

    Spimulator: A spintronic processing-in-memory simulator for racetracks,

    P. Bera, S. Cahoon, S. Bhanja, and A. Jones, “Spimulator: A spintronic processing-in-memory simulator for racetracks,”ACM Transactions on Embedded Computing Systems, vol. 23, no. 6, pp. 1–27, 2024

    2024

  9. [9]

    Robin: Incremental oblique interleaved ecc for reliability improvement in stt-mram caches,

    E. Cheshmikhani, H. Farbeh, and H. Asadi, “Robin: Incremental oblique interleaved ecc for reliability improvement in stt-mram caches,” in Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019, pp. 173–178

    2019

  10. [10]

    A low-cost fault- tolerant racetrack cache based on data compression,

    E. Cheshmikhani, F. Shokouhinia, and H. Farbeh, “A low-cost fault- tolerant racetrack cache based on data compression,”IEEE Transactions on Circuits and Systems II: Express Briefs, 2024

    2024

  11. [11]

    Nonvolatile ferroelectric domain wall memory,

    P. Sharma, Q. Zhang, D. Sando, C. H. Lei, Y . Liu, J. Li, V . Nagarajan, and J. Seidel, “Nonvolatile ferroelectric domain wall memory,”Science advances, vol. 3, no. 6, p. e1700512, 2017

    2017

  12. [12]

    Foosball coding: Correcting shift errors and bit flip errors in 3d racetrack memory,

    S. Archer, G. Mappouras, R. Calderbank, and D. Sorin, “Foosball coding: Correcting shift errors and bit flip errors in 3d racetrack memory,” in2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN). IEEE, 2020, pp. 331–342

    2020

  13. [13]

    Magnetic domain walls: types, processes and applications,

    G. Venkat, D. Allwood, and T. Hayward, “Magnetic domain walls: types, processes and applications,”Journal of Physics D: Applied Physics, vol. 57, no. 6, p. 063001, 2023

    2023

  14. [14]

    Evaluating the impact of racetrack memory misalignment faults on bnns performance,

    L. D. Bereholschi, M. Yayla, J.-J. Chen, K.-H. Chen, and A. Ali Khan, “Evaluating the impact of racetrack memory misalignment faults on bnns performance,” inInternational Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. Springer, 2024, pp. 230–245

    2024

  15. [15]

    Ultralow power and shifting-discretized magnetic racetrack memory device driven by chirality switching and spin current,

    S. Li, X. Lin, P. Li, S. Zhao, Z. Si, G. Wei, B. Koopmans, R. Lavri- jsen, and W. Zhao, “Ultralow power and shifting-discretized magnetic racetrack memory device driven by chirality switching and spin current,” ACS Applied Materials & Interfaces, vol. 15, no. 33, pp. 39 946–39 955, 2023

    2023

  16. [16]

    Streampim: Streaming matrix computation in racetrack memory,

    Y . An, Y . Tang, S. Yi, L. Peng, X. Pan, G. Sun, Z. Luo, Q. Li, and J. Zhang, “Streampim: Streaming matrix computation in racetrack memory,” in2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, 2024, pp. 297–311

    2024

  17. [17]

    Enhanced positional secded: Achieving maximal double-error correction in race- track memories,

    H. M. Abdullah, U. U. Fayyaz, T. Mahmood, and S. Hong, “Enhanced positional secded: Achieving maximal double-error correction in race- track memories,”IEEE Transactions on Magnetics, vol. 60, no. 3, pp. 1–10, 2024. IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, VOL. XX, NO. X, AUGUST 2025 12

    2024

  18. [18]

    Domain wall memory: Physics, materials, and devices,

    D. Kumar, T. Jin, R. Sbiaa, M. Kl ¨aui, S. Bedanta, S. Fukami, D. Rav- elosona, S.-H. Yang, X. Liu, and S. Piramanayagam, “Domain wall memory: Physics, materials, and devices,”Physics Reports, vol. 958, pp. 1–35, 2022

    2022

  19. [19]

    Correcting multiple deletions and insertions in racetrack memory,

    J. Sima and J. Bruck, “Correcting multiple deletions and insertions in racetrack memory,”IEEE Transactions on Information Theory, vol. 69, no. 9, pp. 5619–5639, 2023

    2023

  20. [20]

    Ultralow energy domain wall device for spin- based neuromorphic computing,

    D. Kumar, H. J. Chung, J. Chan, T. Jin, S. T. Lim, S. S. Parkin, R. Sbiaa, and S. Piramanayagam, “Ultralow energy domain wall device for spin- based neuromorphic computing,”ACS nano, vol. 17, no. 7, pp. 6261– 6274, 2023

    2023

  21. [21]

    Domain-stored skyrmion structures for a reading error- detectable racetrack memory,

    T. Karino, D. Shimizu, A. P. Ohki, N. Ikarashi, T. Kato, D. Oshima, and M. Nagao, “Domain-stored skyrmion structures for a reading error- detectable racetrack memory,”arXiv preprint arXiv:2407.08527, 2024

    Pith/arXiv arXiv 2024

  22. [22]

    Toward write opti- mization for skyrmion racetrack memory by skyrmion repermutation,

    T.-Y . Yang, X. Peng, W. Kang, and M.-C. Yang, “Toward write opti- mization for skyrmion racetrack memory by skyrmion repermutation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 6, pp. 1769–1780, 2024

    2024

  23. [23]

    Connected-skyrmions-based racetrack memory,

    T. Nishitani, S. Honda, and H. Itoh, “Connected-skyrmions-based racetrack memory,” in2023 IEEE International Magnetic Conference (INTERMAG). IEEE, 2023, pp. 1–5

    2023

  24. [24]

    A comparative cross-layer study on racetrack memories: Domain wall vs skyrmion,

    W. Kang, B. Wu, X. Chen, D. Zhu, Z. Wang, X. Zhang, Y . Zhou, Y . Zhang, and W. Zhao, “A comparative cross-layer study on racetrack memories: Domain wall vs skyrmion,”ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 16, no. 1, pp. 1–17, 2019

    2019

  25. [25]

    Process variation aware data management for magnetic skyrmions racetrack memory,

    F. Chen, Z. Li, W. Kang, W. Zhao, H. Li, and Y . Chen, “Process variation aware data management for magnetic skyrmions racetrack memory,” in 2018 23rd Asia and South Pacific Design Automation Conference (ASP- DAC). IEEE, 2018, pp. 221–226

    2018

  26. [26]

    Multi-segmented nanowires for vortex magnetic domain wall racetrack memory,

    M. Al Bahri, M. Al Hinaai, and T. Al Harthy, “Multi-segmented nanowires for vortex magnetic domain wall racetrack memory,”Chinese Physics B, vol. 32, no. 12, p. 127508, 2023

    2023

  27. [27]

    Cross-layer racetrack memory design for ultra high density and low power consumption,

    Z. Sun, W. Wu, and H. Li, “Cross-layer racetrack memory design for ultra high density and low power consumption,” inProceedings of the 50th Annual Design Automation Conference, 2013, pp. 1–6

    2013

  28. [28]

    Optimizing data layout for racetrack memory in embedded systems,

    P. Hui, E. H.-M. Sha, Q. Zhuge, R. Xu, and H. Wang, “Optimizing data layout for racetrack memory in embedded systems,” inProceedings of the 28th Asia and South Pacific Design Automation Conference, 2023, pp. 110–115

    2023

  29. [29]

    The gem5 simulator,

    N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashtiet al., “The gem5 simulator,”ACM SIGARCH computer architecture news, vol. 39, no. 2, pp. 1–7, 2011

    2011

  30. [30]

    Spec cpu® 2017 bench- mark suite,

    Standard Performance Evaluation Corporation, “Spec cpu® 2017 bench- mark suite,” https://www.spec.org/cpu2017/, 2017, accessed: April 11, 2025

    2017

  31. [31]

    Cache design with domain wall memory,

    R. Venkatesan, V . J. Kozhikkottu, M. Sharad, C. Augustine, A. Ray- chowdhury, K. Roy, and A. Raghunathan, “Cache design with domain wall memory,”IEEE Transactions on Computers, vol. 65, no. 4, pp. 1010–1024, 2015

    2015

  32. [32]

    Synergistic circuit and system design for energy-efficient and robust domain wall caches,

    S. Motaman, A. Iyengar, and S. Ghosh, “Synergistic circuit and system design for energy-efficient and robust domain wall caches,” inProceed- ings of the 2014 international symposium on Low power electronics and design, 2014, pp. 195–200

    2014

  33. [33]

    Power and energy reduction of racetrack-based caches by exploiting shared shift operations,

    S. S. N. Larimi, M. Kamal, A. Afzali-Kusha, and H. Mahmoodi, “Power and energy reduction of racetrack-based caches by exploiting shared shift operations,” in2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2016, pp. 1–6

    2016

  34. [34]

    Design exploration of racetrack lower-level caches,

    Z. Sun, X. Bi, A. K. Jones, and H. Li, “Design exploration of racetrack lower-level caches,” inProceedings of the 2014 international symposium on Low power electronics and design, 2014, pp. 263–266

    2014

  35. [35]

    Dyrectape: A dynamically reconfigurable cache using domain wall memory tapes,

    A. Ranjan, S. G. Ramasubramanian, R. Venkatesan, V . Pai, K. Roy, and A. Raghunathan, “Dyrectape: A dynamically reconfigurable cache using domain wall memory tapes,” in2015 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2015, pp. 181–186

    2015

  36. [36]

    Evolving skyrmion racetrack memory as energy-efficient last-level cache devices,

    Y .-H. Yang, S.-H. Chen, and Y .-H. Chang, “Evolving skyrmion racetrack memory as energy-efficient last-level cache devices,” inProceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, 2022, pp. 1–6

    2022

  37. [37]

    Ar- chitecting racetrack memory preshift through pattern-based prediction mechanisms,

    A. Colaso, P. Prieto, P. Abad, J. A. Gregorio, and V . Puente, “Ar- chitecting racetrack memory preshift through pattern-based prediction mechanisms,” in2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2019, pp. 273–282

    2019

  38. [38]

    Multilane racetrack caches: Improving efficiency through compression and independent shifting,

    H. Xu, Y . Li, R. Melhem, and A. K. Jones, “Multilane racetrack caches: Improving efficiency through compression and independent shifting,” in The 20th Asia and South Pacific Design Automation Conference. IEEE, 2015, pp. 417–422

    2015

  39. [39]

    Optimizing data placement for reducing shift operations on domain wall memories,

    X. Chen, E. H.-M. Sha, Q. Zhuge, P. Dai, and W. Jiang, “Optimizing data placement for reducing shift operations on domain wall memories,” in Proceedings of the 52nd Annual Design Automation Conference, 2015, pp. 1–6

    2015

  40. [40]

    Efficient data placement for improving data access performance on domain-wall memory,

    X. Chen, E. H.-M. Sha, Q. Zhuge, C. J. Xue, W. Jiang, and Y . Wang, “Efficient data placement for improving data access performance on domain-wall memory,”IEEE Transactions on Very Large Scale Integra- tion (VLSI) Systems, vol. 24, no. 10, pp. 3094–3104, 2016

    2016

  41. [41]

    Shiftsreduce: Minimizing shifts in racetrack memory 4.0,

    A. A. Khan, F. Hameed, R. Bl ¨asing, S. S. Parkin, and J. Castrillon, “Shiftsreduce: Minimizing shifts in racetrack memory 4.0,”ACM Trans- actions on Architecture and Code Optimization (TACO), vol. 16, no. 4, pp. 1–23, 2019

    2019

  42. [42]

    Generalized data placement strategies for racetrack memories,

    A. A. Khan, A. Goens, F. Hameed, and J. Castrillon, “Generalized data placement strategies for racetrack memories,” in2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2020, pp. 1502–1507

    2020

  43. [43]

    Fast- track cache: a huge racetrack memory l1 data cache,

    H. T ´arrega, A. Valero, V . Lorente, S. Petit, and J. Sahuquillo, “Fast- track cache: a huge racetrack memory l1 data cache,” inProceedings of the 36th ACM International Conference on Supercomputing, 2022, pp. 1–12

    2022

  44. [44]

    Blendcache: An energy and area ef- ficient racetrack last-level-cache architecture,

    F. Hameed and J. Castrillon, “Blendcache: An energy and area ef- ficient racetrack last-level-cache architecture,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 12, pp. 5288–5298, 2022

    2022

  45. [45]

    Destiny: A comprehensive tool with 3d and multi-level cell memory modeling capability,

    S. Mittal, R. Wang, and J. Vetter, “Destiny: A comprehensive tool with 3d and multi-level cell memory modeling capability,”Journal of Low Power Electronics and Applications, vol. 7, no. 3, p. 23, 2017. Elham Cheshmikhaniis an assistant professor at the Department of Computer Science and Engineer- ing at Shahid Beheshti University, Tehran, Iran. She also s...

    2017