Pith. sign in

REVIEW 3 major objections 5 minor 56 references

Monophonic Audio Synthesizer Using FPGAs

T0 review · 3 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read The paper's central claim is that an FPGA-based direct digital synthesis core, using a phase accumulator, LUT oscillators, and delta-sigma output, produces an audible 440 Hz A note from a single SMA pin.

desk verdict An honest student project report that overstates its own success; the synth never worked as claimed and the only demo is an unmeasured button-triggered tone. read the letter →

arxiv 2608.10116 v1 pith:UG3ZEJDW submitted 2026-08-10 cs.AR cs.SD

Michael Smith , D.G. Perera This is my paper · ORCID
classification cs.ARcs.SD
keywords FPGAaudiosynthesisdirectdigitalphaseaccumulatorlook-uptableoscillatordelta-sigmamodulationmonophonicsynthesizerMIDI-to-frequencyconversion
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This project report sets out to show that a monophonic audio synthesizer can be built from FPGA logic using direct digital synthesis. The design routes MIDI-style note messages into 32-bit tuning words that drive phase accumulators, and each accumulator indexes look-up tables that generate sine, square, sawtooth, or triangle waveforms. The signal path continues through an ADSR envelope, two lowpass filters, and a delta-sigma modulator that emits a one-bit stream from an SMA connector. The central empirical claim is that, with the envelope and filters removed to meet timing closure and a fixed note constant substituted for UART input, holding a board button produces an audible 440 Hz A note through the analog output stage. A sympathetic reader would take this as evidence that the FPGA-based synthesis core and delta-sigma audio output path are fundamentally sound.

What carries the argument

The load-bearing object is the phase accumulator: a 32-bit unsigned register incremented every 100 MHz clock cycle by a tuning word $M$, producing an output frequency $f_{out} = M \cdot 100\text{ MHz} / 2^{32}$, a step size of about 0.0233 Hz. The upper bits of the accumulator index the oscillator lookup tables (2048 entries for a half sine wave, with the top bit controlling mirroring and inversion; the other three waveforms are read directly from the accumulator). The output mechanism is a delta-$\sigma$ modulator that reduces the 32-bit audio sample to a 1-bit stream at 100 MHz, giving an oversampling ratio of roughly 2083 over the 48 kHz sample rate and pushing quantization noise outside the audible band, where the single-pole RC filter attenuates it.

What would settle it

Reproduce the final demo while leaving the SMA pins in their default differential-pair configuration; if no 440 Hz tone reaches the speakers, the output-stage assumption is the crux. A more direct check is to probe the SMA connector with an oscilloscope while the south button is held: absence of a roughly 1.5 V peak square wave at 440 Hz would refute the paper's central success claim.

Watch

Extended reading notes

Core claim

The paper's central discovery is that a phase-accumulator DDS core with LUT-based oscillators and a 1-bit delta-$\sigma$ output can produce audible audio from an FPGA's SMA pin without a dedicated audio codec. The frequency path rests on the relation $f_{out} = M \cdot f_{clk} / 2^{32}$, with $M$ a 32-bit tuning word retrieved from a 128-entry ROM built from MIDI note numbers; the oscillator path uses a 2048-entry half-sine LUT with mirror-and-invert reconstruction, plus direct phase-accumulator mappings for sawtooth, triangle, and square waves. The delta-$\sigma$ stage oversamples the 48 kHz audio stream at 100 MHz, an oversampling ratio near 2083, and the external RC filter removes the resulting out-of-band quantization noise. The demonstration runs with a constant MIDI note (A, 440 Hz), button-triggered output, and button-selected waveform, because the UART link to a host PC never transferred data and the envelope and filter modules were removed after timing constraint failures.

Load-bearing premise

The design assumes the board's SMA GPIO pins can be reconfigured from differential-pair mode to single-ended digital output with a voltage high enough to drive the external analog stage; the paper reports the default configuration blocked this and the fix capped output at 1.5 V, forcing an analog voltage-divider redesign.

Editorial extensions

If this is right

  • A phase-accumulator DDS core with LUT oscillators is sufficient to generate the four classic synthesizer waveforms in FPGA fabric using modest block RAM.
  • Delta-sigma modulation from a 48 kHz audio stream at 100 MHz lets a single FPGA pin carry audio, with only an RC filter and op-amp needed for line-level output.
  • The tuning-word ROM and phase-accumulator width set frequency resolution near 0.0233 Hz, which is fine enough for equal-temperament note intervals.
  • The same synthesis core can be retargeted to higher frequencies by changing the clock or tuning-word LUT, so the audio application is one instance of a general DDS building block.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The UART failure is independent of the synthesis chain; swapping the host link for a microcontroller or I2C interface should restore live MIDI control without touching the oscillator or output path.
  • Pipelining the envelope and filter multipliers at the sample-rate boundary (2083 clock cycles per sample) should recover timing closure, as the paper identifies; this is a straightforward engineering fix rather than a conceptual obstacle.
  • A frequency counter on the SMA output could verify tuning accuracy; the 0.0233 Hz step implies the 440 Hz note should be stable to within a fraction of a cent.
  • The 128-entry MIDI tuning-word ROM could be replaced by a small arithmetic unit that computes $M = \lfloor f_{note} \cdot 2^{32} / f_{clk}\rfloor$, making the design clock-agnostic and removing the ROM.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper describes work toward an FPGA-based monophonic audio synthesizer on a Xilinx AC701 board. It presents designs for a UART/MIDI parser, a MIDI-to-tuning-word lookup table, four oscillator modules, an ADSR envelope, velocity scaling, two lowpass filters, and a delta-sigma output stage, along with an external RC filter and op-amp buffer. The narrative reports several difficulties: an SMA voltage-standard problem, timing constraint failures that led to removal of the ADSR and both filter modules, and a UART communication failure that was never resolved. The final deployment is a constant MIDI note (A at 440 Hz) selected by a hard-coded constant, routed through the oscillator selector and delta-sigma modulator, and triggered by a GPIO button. The paper concludes with lessons about pipelining, serial communication, and a large block of future-work statements citing prior work from the same research group.

Significance. If the claimed demonstration were fully measured and reproducible, it would be a modest engineering example of direct digital synthesis with delta-sigma audio output on an FPGA. However, as written, the central claim of a completed digital synthesizer is not supported: MIDI control never worked, the ADSR envelope and both lowpass filters were removed, and the only reported empirical result is an anecdotal audible tone. No frequency measurement, waveform capture, amplitude characterization, or independent verification is provided. The significance of the paper as a research contribution is therefore low.

major comments (3)
  1. [Timing Constraint Failure; UART/COM Failure; Design Success] The abstract and introduction promise a synthesizer with MIDI control, an ADSR envelope, user-controllable filtering, and anti-aliasing filtering. The sections on design difficulties explicitly state that the ADSR envelope and both lowpass filters were removed because of timing constraint failures and that UART/MIDI communication never worked. The final design therefore consists only of a hard-coded 440 Hz note passed through the oscillator selector and delta-sigma modulator. The central claim of creating a digital synthesizer is unsupported by the delivered and tested design.
  2. [Design Success] The load-bearing empirical claim is that holding the south user button outputs an A note at 440 Hz from the SMA connector. No measurement is reported: there is no frequency counter reading, oscilloscope trace, FFT, recorded audio, or amplitude/SNR measurement. The statement that the tone was 'observed' through speakers is anecdotal, and the specific frequency, waveform quality, and correct operation of the analog RC filter and buffer are not verified.
  3. [Project Development (throughout)] No source files, bitstream, or synthesis/implementation reports are provided. The design relies on MATLAB-generated LUTs, Vivado IP, and a Python script, but none of these artifacts are included, and no resource utilization or quantitative timing slack figures are given beyond the qualitative statement that path delays 'far exceeded' constraints. Independent reproduction or verification of the claimed hardware behavior is therefore impossible.
minor comments (5)
  1. [Digital Synthesis] There is a typo: 'Direst digital synthesis' should be 'Direct digital synthesis.'
  2. [MIDI note Frequency Conversion] The phrase 'or The clock time also had to be determined' contains a stray 'or' and broken capitalization; it should read as a single sentence.
  3. [References] Reference [57] is empty and is never cited in the text; it should be removed or filled.
  4. [Discussions/Conclusion] The future-work paragraph abruptly introduces a 'mini X-ray detector front end' topic that is unrelated to anything else in the manuscript; this appears to be a copy-paste artifact and should be corrected.
  5. [Design Success] The paper would be substantially stronger if the final tone were characterized with at least an oscilloscope screenshot or a recorded audio file with a measured frequency marker; currently the only evidence is subjective listening.

Circularity Check

1 steps flagged · score 2.0 of 10

No circularity in the hardware derivation; one minor self-cited motivational claim lowers the score to 2.

  1. other [Discussions/Conclusion, final paragraph before References (paragraph beginning 'This work is inspired by the digital design research group at UCCS', refs [3]-[41]).]
    "Their analyses [3],[4] show that FPGA-based embedded systems are currently the best option to support applications and techniques, such as the ones presented in this report."

    References [3] and [4] are authored or co-authored by D.G. Perera, an author of this paper, and the surrounding paragraph extends the same 'best avenue' claim using [5]-[41], all from the same UCCS group. The motivational assertion that FPGAs are the best option is therefore supported by the authors' own prior conclusions rather than by an independent external benchmark. This is not load-bearing for the technical result: the 440 Hz demo follows from the standard DDS tuning-word formula, the generated LUTs, and direct listening observation, not from [3]-[41]. It is a framing-level, minor self-citation issue rather than a derivation that assumes its conclusion.

full rationale

The paper's central claim is an engineering demonstration, not a mathematical derivation: an AC701 FPGA runs a phase-accumulator/square-wave/delta-sigma chain with a hard-coded MIDI note constant and produces an audible tone. No parameter is fitted to the output and then renamed as a prediction; LUT contents (MIDI tuning words, sine half-wave, filter coefficients) are generated in MATLAB from standard formulas and stated assumptions (100 MHz clock, 32-bit accumulator, f_out = M*CLK/2^N, 48 kHz audio rate), and the analog RC filter is a conventional external low-pass/buffer. The paper openly reports that the ADSR, both filters, and UART/MIDI path were removed, so the abstract's broader synthesizer claim is not fully supported empirically; that is a completeness/evidence problem, not circularity. The only circularity-adjacent element is the concluding motivational assertion that FPGA-based systems are 'the best option,' supported by a long list of the authors' own prior papers; this does not feed into the observed 440 Hz result. Score 2 reflects one minor, non-load-bearing self-citation; no fitted-input-as-prediction, uniqueness-import, or ansatz-smuggling pattern is present.

Assumptions & free parameters 5 free parameters · 4 assumptions · 0 invented entities

The central claim rests on standard DDS math and board-level assumptions about the FPGA. The free parameters are design choices, not fitted values, but they affect the correctness of the frequency and filter responses. There are no invented physical entities.

free parameters (5)
  • system clock frequency = 100 MHz
    Chosen by hand; the MIDI-to-tuning-word LUT is generated for this specific clock, so changing it requires regenerating the LUT.
  • phase accumulator bit width = 32 bits
    Chosen to achieve a frequency step of 0.0233 Hz; the author notes 24 bits would also suffice.
  • sine LUT depth = 2048 entries
    Stores one half-period; sets the phase truncation to 11 bits.
  • audio sample rate = 48 kHz
    Used to generate the Butterworth filter coefficients and the delta-sigma oversampling ratio.
  • ADSR max times = attack/decay 5 s, release 10 s
    Chosen scaling limits, stored as 256-entry exponential LUTs.
assumptions (4)
  • standard math DDS output frequency follows f_out = M * CLK / 2^N
    Taken from the Analog Devices DDS tutorial [2], used to size the tuning word and assess frequency step.
  • domain assumption The AC701 user SMA GPIOs can be configured as single-ended outputs at a valid voltage bank standard
    Initially violated: the SMA pins default to a differential pair and required constraint changes that lowered the max voltage to 1.5 V.
  • domain assumption The 100 MHz clock can complete the multiplier-heavy combinational logic within one period
    Violated: implementation showed timing constraint failures in the envelope and filter modules, forcing their removal.
  • domain assumption A single RC lowpass filter plus op-amp buffer is sufficient to reconstruct the delta-sigma bitstream into audible audio without the digital anti-aliasing filter
    Assumed in the analog output stage; the paper acknowledges the digital anti-aliasing filter would be needed for better quality.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Monophonic Audio Synthesizer Using FPGAs." pith.science (2026). https://pith.science/paper/UG3ZEJDW

@misc{pith2026260810116,
  author       = {Pith},
  title        = {Pith review of: Monophonic Audio Synthesizer Using FPGAs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/UG3ZEJDW}},
  note         = {Machine review of arXiv:2608.10116}
}
read the original abstract

Signal synthesis is used in every aspect of the electronics world, where sinusoidal waveforms are used to perform functions such as clocking, signal transmission, feedback controls, and other applications. Digital synthesis is the method of approximating sinusoidal waveforms using digital logic, where the waveform is approximated to an accurate degree at a specific frequency which can be either implemented digitally or converted into the analog domain for use elsewhere. This project details the creation of a digital synthesizer commonly used for professional audio applications through the implementation of hardware in an FPGA.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

56 extracted references · 16 canonical work pages

  1. [1]

    MIDI Tutorial,

    B. J., "MIDI Tutorial," Sparkfun Electronics, [Online]. Available: https://learn.sparkfun.com/tutorials/midi- tutorial/all#implementing-midi. [Accessed 13 May 2026]

    work page 2026

  2. [2]

    A Technical Tutorial on Digital Signal Synthesis,

    Analog Devices, "A Technical Tutorial on Digital Signal Synthesis," Analog Devices, Inc., 1999

    work page 1999

  3. [3]

    Analysis of Single-Chip Hardware Support for Mobile and Embedded Applications,

    D.G. Perera and K.F. Li, "Analysis of Single-Chip Hardware Support for Mobile and Embedded Applications," in Proc. of IEEE Pacific Rim Int. Conf. on Communication, Computers, and Signal Processing, (PacRim’13), pp. 369-376, Victoria, BC, Canada, August 2013

    2013

  4. [4]

    Analysis of Computation Models and Application Characteristics Suitable for Reconfigurable FPGAs

    D.G. Perera and K.F. Li, “Analysis of Computation Models and Application Characteristics Suitable for Reconfigurable FPGAs”, in Proc. of 10th IEEE Int. Conf. on P2P, Parallel, Grid, Cloud, and Internet Computing, (3PGCIC’15), pp. 244-247, Krakow, Poland, Nov. 2015

    2015

  5. [5]

    Optimized Hardware Accelerators for Data Mining Applications on Embedded Platform: Case Study Principal Component Analysis,

    S.N. Shahrouzi and D.G. Perera, "Optimized Hardware Accelerators for Data Mining Applications on Embedded Platform: Case Study Principal Component Analysis," Elsevier Journal on Microprocessor and Microsystems (MICPRO), vol. 65, pp. 79-96, March 2019

    2019

  6. [6]

    Embedded Hardware Solution for Principal Component Analysis,

    D.G. Perera and K.F. Li, "Embedded Hardware Solution for Principal Component Analysis," in Proc. of IEEE Pacific Rim Int. Conf. on Communication, Computers, and Signal Processing, (PacRim’11), pp.730 -735, Victoria, BC, Canada, August 2011

    work page 2011

  7. [7]

    Hardware Acceleration for Similarity Computations of Feature Vectors,

    D.G. Perera and Kin F. Li, “Hardware Acceleration for Similarity Computations of Feature Vectors,” IEEE Canadian Journal of Electrical and Computer Engineering, (CJECE), vol. 33, no. 1, pp. 21 -30, Winter 2008

    2008

  8. [8]

    On-Chip Hardware Support for Similarity Measures,

    D.G. Perera and K.F. Li, “On-Chip Hardware Support for Similarity Measures,” in Proc. of IEEE Pacific Rim Int. Conf. on Communication, Computers, and Signal Processing, (PacRim’07), pp. 354 -358, Victoria, BC, Canada, August 2007

    work page 2007

Show all 56 references
  1. [9]

    An Investigation of Chip-Level Hardware Support for Web Mining,

    K.F. Li and D.G. Perera, “An Investigation of Chip-Level Hardware Support for Web Mining,” in Proc. of IEEE Int. Symp. on Data Mining and Information Retrieval, (DMIR’07), pp. 341 -348, Niagara Falls, ON, Canada, May 2007

    2007

  2. [10]

    A Hardware Collective Intelligent Agent

    K.F. Li and D.G. Perera, “A Hardware Collective Intelligent Agent”, Transactions on Computational Collective Intelligence, LNCS 7776, Springer, pp. 45-59, 2013

    2013

  3. [11]

    Optimizing Density-Based Ant Colony Stream Clustering Using FPGA-Based Hardware Accelerator

    J.R. Graf and D.G. Perera, “Optimizing Density-Based Ant Colony Stream Clustering Using FPGA-Based Hardware Accelerator”, in Proc. Of IEEE Int. Symp. on Circuits and Systems (ISCAS’23), 5-page manuscript, Monterey, California, May 2023

    2023

  4. [12]

    Chip-Level and Reconfigurable Hardware for Data Mining Applications,

    D.G. Perera, “Chip-Level and Reconfigurable Hardware for Data Mining Applications,” PhD Dissertation, Department of Electrical & Computer Engineering, University of Victoria, Victoria, BC, Canada, April 2012

    2012

  5. [13]

    Optimized Embedded and Reconfigurable Hardware Architectures and Techniques for Data Mining Applications on Mobile Devices

    S. Navid Shahrouzi, "Optimized Embedded and Reconfigurable Hardware Architectures and Techniques for Data Mining Applications on Mobile Devices", PhD Dissertation, Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, December 2018

    2018

  6. [14]

    Optimizing Density-Based Ant Colony Stream Clustering Using FPGAs

    J. Graf, "Optimizing Density-Based Ant Colony Stream Clustering Using FPGAs", MSc Thesis, Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, CO, USA, March 2022

    2022

  7. [15]

    Efficient Embedded Architectures for Model Predictive Controller for Battery Cell Management in Electric Vehicles

    A.K. Madsen and D.G. Perera, “Efficient Embedded Architectures for Model Predictive Controller for Battery Cell Management in Electric Vehicles”, EURASIP Journal on Embedded Systems, SpringerOpen, vol. 2018, article no. 2, 36-page manuscript, July 2018

    2018

  8. [16]

    An Optimized FPGA-Based Hardware Accelerator for Physics- Based EKF for Battery Cell Management

    A.K. Madsen, M.S. Trimboli, and D.G. Perera, “An Optimized FPGA-Based Hardware Accelerator for Physics- Based EKF for Battery Cell Management”, in Proc. of IEEE Int,l Symp, on Circuits and Systems, (ISCAS’20), 5-page manuscript, Seville, Spain, May 2020

    2020

  9. [17]

    Towards Composing Efficient FPGA-Based Hardware Accelerators for Physics-Based Model Predictive Control Smart Sensor for HEV Battery Cell Management

    A.K. Madsen and D.G. Perera, “Towards Composing Efficient FPGA-Based Hardware Accelerators for Physics-Based Model Predictive Control Smart Sensor for HEV Battery Cell Management”, IEEE ACCESS, (Open Access Journal in IEEE), pp. 106141-106171, 25th September 2023

    2023

  10. [18]

    Composing Optimized Embedded Software Architectures for Physics-Based EKF-MPC Smart Sensor for Li-Ion Battery Cell Management

    A.K. Madsen and D.G. Perera, “Composing Optimized Embedded Software Architectures for Physics-Based EKF-MPC Smart Sensor for Li-Ion Battery Cell Management”, Sensors, MDPI open access journal, Intelligent Sensors Section, 21-page manuscript, vol. 22, no. 17, 26th August 2022. 14

    2022

  11. [19]

    Optimized Embedded Architectures for Model Predictive Control Algorithms for Battery Cell Management Systems in Electric Vehicles

    A.K. Madsen, “Optimized Embedded Architectures for Model Predictive Control Algorithms for Battery Cell Management Systems in Electric Vehicles”; PhD Dissertation, Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, August 2020

    2020

  12. [20]

    An FPGA-Based Linear Kalmann Filter for a Two-Phase Buck Converter Application

    D. Abillar, "An FPGA-Based Linear Kalmann Filter for a Two-Phase Buck Converter Application", MSc Thesis, Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, CO, USA, April 2024

    2024

  13. [21]

    Efficient FPGA-Based Reconfigurable Accelerators for SIMON Cryptographic Algorithm on Embedded Platforms

    A. Alkamil and D.G. Perera, “Efficient FPGA-Based Reconfigurable Accelerators for SIMON Cryptographic Algorithm on Embedded Platforms”, in Proceedings of the IEEE International Conferences on Reconfigurable Computing and FPGAs, (ReConFig’19), 8-page manuscript, Cancun, Mexico,...

    2019

  14. [22]

    Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices

    A. Alkamil and D.G. Perera, “Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices”, IEEE Access, Open Access Journal in IEEE, vol. 8, pp: 221720 – 221742, 10th December 2020

    2020

  15. [23]

    Dynamic Reconfigurable Architectures to Improve Performance and Scalability of Cryptosystems on Embedded Systems

    A. Alkamil, “Dynamic Reconfigurable Architectures to Improve Performance and Scalability of Cryptosystems on Embedded Systems”, PhD Dissertation, Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, 5th February 2021

    2021

  16. [24]

    An FPGA-Based Hardware Accelerator for K-Nearest Neighbor Classification for Machine Learning on Mobile Devices

    M.A. Mohsin and D.G. Perera, “An FPGA-Based Hardware Accelerator for K-Nearest Neighbor Classification for Machine Learning on Mobile Devices”, in Proceedings of the IEEE/ACM International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, (HEART’18), ...

    2018

  17. [25]

    An Efficient FPGA-Based Hardware Accelerator for Convex Optimization- Based SVM Classifier for Machine Learning on Embedded Platforms

    S. Ramadurgam and D.G. Perera, “An Efficient FPGA-Based Hardware Accelerator for Convex Optimization- Based SVM Classifier for Machine Learning on Embedded Platforms”, Electronics, MDPI open access journal, 36-page manuscript, vol. 10, no. 11, 31st May 2021

    2021

  18. [26]

    A Systolic Array Architecture for SVM Classifier for Machine Learning on Embedded Devices

    S. Ramadurgam and D.G. Perera, “A Systolic Array Architecture for SVM Classifier for Machine Learning on Embedded Devices”, in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS’23), 5 -page manuscript, Monterey, California, May 2023

    2023

  19. [27]

    FPGA-based Hardware Accelerator for Bottleneck Residual Blocks of MobileNetV2 Convolutional Neural Networks

    Jordi P. Miró, Mokhles A. Mohsin, Arkan Alkamil and Darshika G. Perera, “FPGA-based Hardware Accelerator for Bottleneck Residual Blocks of MobileNetV2 Convolutional Neural Networks”, in Proceedings of the IEEE Mid-West Symposium on Circuits and Systems (MWCAS’25), 5-page manus...

    2025

  20. [28]

    An FPGA-Based Hardware Accelerator for K-Nearest Neighbor Classification for Machine Learning

    M. A. Mohsin, "An FPGA-Based Hardware Accelerator for K-Nearest Neighbor Classification for Machine Learning", MSc Thesis, Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, CO, USA, December 2017

    2017

  21. [29]

    Optimized Embedded Architectures and Techniques for Machine Learning Algorithms for On-Chip AI Acceleration

    S. Ramadurgam, “Optimized Embedded Architectures and Techniques for Machine Learning Algorithms for On-Chip AI Acceleration”, PhD Dissertation, Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, 12th February 2021

    2021

  22. [30]

    FPGA-Based Accelerators for Convolutional Neural Networks on Embedded Devices

    J. P. Miro, " FPGA-Based Accelerators for Convolutional Neural Networks on Embedded Devices", MSc Thesis, Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, CO, USA, May 2020

    2020

  23. [31]

    An Efficient Hardware Accelerator for Binary Residual Neural Network Using FPGAs

    R. Wallace, "An Efficient Hardware Accelerator for Binary Residual Neural Network Using FPGAs ", MSc Thesis, Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, CO, USA, May 2026

    2026

  24. [32]

    Intelligent Cognitive Radio Architecture Applying Machine Learning and Reconfigurability

    J. Nurmi and D.G. Perera, “Intelligent Cognitive Radio Architecture Applying Machine Learning and Reconfigurability” in Proc. of IEEE Nordic Circuits and Systems (NorCAS'21) Conf., 6 -page manuscript, Oslo, Norway, October 2021

    2021

  25. [33]

    High-Level Synthesis Based FPGA Accelerator for GPS Signal Image Feature Extraction

    Kevin Young and Darsika G. Perera, “High-Level Synthesis Based FPGA Accelerator for GPS Signal Image Feature Extraction”, in Proceedings of the IEEE Mid-West Symposium on Circuits and Systems (MWCAS’25), 5-page manuscript, Lansing MI, August 2025

    2025

  26. [34]

    Reconfigurable Architectures for Data Analytics on Next-Generation Edge-Computing Platforms

    D.G. Perera, “Reconfigurable Architectures for Data Analytics on Next-Generation Edge-Computing Platforms”, Featured Article, IEEE Canadian Review, vol. 33, no. 1, Spring 2021. DOI: 10.1109/MICR.2021.3057144

    2021

  27. [35]

    Composing Efficient Computational Models for Real -Time Processing on Next-Generation Edge-Computing Platforms

    M.A. Mohsin, S.N. Shahrouzi, and D.G. Perera, “Composing Efficient Computational Models for Real -Time Processing on Next-Generation Edge-Computing Platforms” IEEE ACCESS, (Open Access Journal in IEEE), 30-page manuscript, 13th February 2024. 15

    2024

  28. [36]

    High-Level Synthesis-Based FPGA Hardware Architecture for PCA+SVM for Real-Time Processing on Edge Computing Platforms

    Mokhles A. Mohsin, and Darshika G. Perera, “High-Level Synthesis-Based FPGA Hardware Architecture for PCA+SVM for Real-Time Processing on Edge Computing Platforms” IEEE ACCESS, (Open Access Journal in IEEE), 24-page manuscript, 18th December 2025. DOI: 10.1109/ACCESS.2025.364576

    2025

  29. [37]

    FPGA-Based Hardware Architecture for Sequence Alignment by Genetic Algorithm

    Laura H. Garcia, Arkan Alkamil, Mokhles A. Mohsin, Johannes Menzel and Darshika G. Perera, “FPGA-Based Hardware Architecture for Sequence Alignment by Genetic Algorithm”, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’25), 5-page manuscript, ...

    2025

  30. [38]

    An FPGA-Based Hardware Accelerator for Sequence Alignment by Genetic Algorithm

    L. H. Garcia, "An FPGA-Based Hardware Accelerator for Sequence Alignment by Genetic Algorithm", MSc Thesis, Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, CO, USA, December 2019

    2019

  31. [39]

    Neuromorphic Sentiment Analysis Using Spiking Neural Networks

    R.K. Chunduri and D.G. Perera, “Neuromorphic Sentiment Analysis Using Spiking Neural Networks”, Sensors, MDPI open access journal, Sensing and Imaging Section, 24-page manuscript, vol. 23, no. 7701, 6th September 2023

    2023

  32. [40]

    Analysis of Generalized Hebbian Learning Algorithm for Neuromorphic Hardware Using Spinnaker

    S. Sharma and D. G. Perera, “Analysis of Generalized Hebbian Learning Algorithm for Neuromorphic Hardware Using Spinnaker” 8-page manuscript, https://doi.org/10.48550/arXiv.2411.11575

    doi arXiv

  33. [41]

    High-Level Synthesis-Based FPGA Hardware Accelerator for Generalized Hebbian Learning Algorithm for Neuromorphic Computing

    S. Sharma, and D.G. Perera, “High-Level Synthesis-Based FPGA Hardware Accelerator for Generalized Hebbian Learning Algorithm for Neuromorphic Computing” Electronics, MDPI open access journal, 21 -page manuscript, vol. 15, no. 8: 1725. 18th April 2026; https://doi.org/10.3390/e...

    2026 doi

  34. [42]

    A Fast and Scalable FPGA-Based Parallel Processing Architecture for K-Means Clustering for Big Data Analysis

    R. Raghavan and D.G. Perera, “A Fast and Scalable FPGA-Based Parallel Processing Architecture for K-Means Clustering for Big Data Analysis”, in Proceedings of the IEEE Pacific Rim International Conference on Communications, Computers, and Signal Processing, (PacRim’17), pp. 1 ...

    2017

  35. [43]

    Parallel Computation of Similarity Measures Using an FPGA-Based Processor Array,

    D.G. Perera and Kin F. Li, “Parallel Computation of Similarity Measures Using an FPGA-Based Processor Array,” in Proceedings of 22nd IEEE International Conference on Advanced Information Networking and Applications, (AINA’08), pp. 955-962, Okinawa, Japan, March 2008

    2008

  36. [44]

    A Fast and Scalable Hardware Architecture for K-Means Clustering for Big Data Analysis

    R. Raghavan, "A Fast and Scalable Hardware Architecture for K-Means Clustering for Big Data Analysis", MSc Thesis, (Supervisor Dr. Darshika G. Perera), Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, CO, USA, May 2016

    2016

  37. [45]

    A Design Methodology for Mobile and Embedded Applications on FPGA-Based Dynamic Reconfigurable Hardware

    D.G. Perera and K.F. Li, “A Design Methodology for Mobile and Embedded Applications on FPGA-Based Dynamic Reconfigurable Hardware”, International Journal of Embedded Systems, (IJES), Inderscience publishers, 23-page manuscript, vol. 11, no. 5, Sept. 2019

    2019

  38. [46]

    Analysis of FPGA-Based Reconfiguration Methods for Mobile and Embedded Applications

    D.G. Perera, “Analysis of FPGA-Based Reconfiguration Methods for Mobile and Embedded Applications”, in Proceedings of 12th ACM FPGAWorld International Conference, (FPGAWorld’15), pp. 15-20, Stockholm, Sweden, September 2015

    2015

  39. [47]

    Discrepancy in Execution Time: Static Vs. Dynamic Reconfigurable Hardware

    D.G. Perera and K.F. Li, “Discrepancy in Execution Time: Static Vs. Dynamic Reconfigurable Hardware”, IEEE Pacific Rim Int. Conf. on Communications, Computers, and Signal Processing, (PacRim’24), 6 -page manuscript, Victoria, BC, Canada, August 2024

    2024

  40. [48]

    FPGA-Based Reconfigurable Hardware for Compute Intensive Data Mining Applications

    D.G. Perera and Kin F. Li, “FPGA-Based Reconfigurable Hardware for Compute Intensive Data Mining Applications”, in Proc. of 6th IEEE Int. Conf. on P2P, Parallel, Grid, Cloud, and Internet Computing, (3PGCIC’11), pp. 100-108, Barcelona, Spain, October 2011

    2011

  41. [49]

    Similarity Computation Using Reconfigurable Embedded Hardware,

    D.G. Perera and Kin F. Li, “Similarity Computation Using Reconfigurable Embedded Hardware,” in Proceedings of 8th IEEE International Conference on Dependable, Autonomic, and Secure Computing (DASC’09), pp. 323-329, Chengdu, China, December 2009

    2009

  42. [50]

    Dynamic Partial Reconfigurable Hardware Architecture for Principal Component Analysis on Mobile and Embedded Devices

    S.N. Shahrouzi and D.G. Perera, “Dynamic Partial Reconfigurable Hardware Architecture for Principal Component Analysis on Mobile and Embedded Devices”, EURASIP Journal on Embedded Systems, SpringerOpen, vol. 2017, article no. 25, 18-page manuscript, 21st February 2017

    2017

  43. [51]

    HDL Code Optimization: Impact on Hardware Implementations and CAD Tools

    S.N Shahrouzi and D.G. Perera, “HDL Code Optimization: Impact on Hardware Implementations and CAD Tools”, in Proc. of IEEE Pacific Rim Int. Conf. on Communications, Computers, and Signal Processing, (PacRim’19), 9-page manuscript, Victoria, BC, Canada, August 2019

    2019

  44. [52]

    HDL Code Variation: Impact on FPGA Performance Metrics and CAD Tools

    I.D. Atwell and D.G. Perera, “HDL Code Variation: Impact on FPGA Performance Metrics and CAD Tools”, IEEE Pacific Rim Int. Conf. on Communications, Computers, and Signal Processing, (PacRim’24), 6 -page manuscript, Victoria, BC, Canada, August 2024. 16

    2024

  45. [53]

    Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs

    S.N. Shahrouzi, A. Alkamil, and D.G. Perera, “Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs”, IEEE Access, Open Access Journal in IEEE, vol. 8, no. 1, pp. 91531- 91545, 14th May 2020

    2020

  46. [54]

    An Efficient Embedded Multi-Ported Memory Architecture for Next- Generation FPGAs

    S.N. Shahrouzi and D.G. Perera, “An Efficient Embedded Multi-Ported Memory Architecture for Next- Generation FPGAs”, in Proceedings of 28th Annual IEEE International Conferences on Application-Specific Systems, Architectures, and Processors, (ASAP’17), pp. 83-90, Seattle, WA, ...

    2017

  47. [55]

    An Efficient FPGA-Based Memory Architecture for Compute-Intensive Applications on Embedded Devices

    S.N. Shahrouzi and D.G. Perera, “An Efficient FPGA-Based Memory Architecture for Compute-Intensive Applications on Embedded Devices”, in Proceedings of the IEEE Pacific Rim International Conference on Communications, Computers, and Signal Processing, (PacRim’17), pp. 1-8, Vict...

    2017

  48. [56]

    Optimized Counter-Based Multi-Ported Memory Architectures for Next- Generation FPGAs

    S.N. Shahrouzi and D.G. Perera, “Optimized Counter-Based Multi-Ported Memory Architectures for Next- Generation FPGAs”, in Proceedings of the 31st IEEE International Systems-On-Chip Conference, (SOCC’18), pp. 106-111, Arlington, V A, Sep. 2018. [57]

    2018

Pith tools

Reviewed August 14, 2026 · model on record in the stance chip above.