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Demystifying the Communication Characteristics for Distributed Transformer Models

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arxiv 2408.10197 v1 pith:VAPVKBU4 submitted 2024-08-19 cs.DC cs.AI

classification cs.DCcs.AI
keywords modelscommunicationtransformerdistributedtrainingarchitecturefurtherlanguage
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Deep learning (DL) models based on the transformer architecture have revolutionized many DL applications such as large language models (LLMs), vision transformers, audio generation, and time series prediction. Much of this progress has been fueled by distributed training, yet distributed communication remains a substantial bottleneck to training progress. This paper examines the communication behavior of transformer models - that is, how different parallelism schemes used in multi-node/multi-GPU DL Training communicate data in the context of transformers. We use GPT-based language models as a case study of the transformer architecture due to their ubiquity. We validate the empirical results obtained from our communication logs using analytical models. At a high level, our analysis reveals a need to optimize small message point-to-point communication further, correlations between sequence length, per-GPU throughput, model size, and optimizations used, and where to potentially guide further optimizations in framework and HPC middleware design and optimization.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Diagnosing Overhead in Dispatch Operations: Cross-architecture Observatory

    cs.DC 2026-05 unverdicted novelty 6.0 of 10

    Expert-parallel scaling leaves per-expert routing imbalance flat; mock-token benchmarks overestimate real-text imbalance and fake a batch-size trend; architectures split into data-resilient (MHA, Mamba-2) and persiste...

  2. Characterizing Communication Patterns in Distributed Large Language Model Inference

    cs.DC 2025-07 conditional novelty 5.0 of 10

    Communication volume and latency of LLM inference are characterized and modeled for tensor, pipeline, and hybrid parallelism, showing that decode-stage operations dominate inter-GPU traffic.

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