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REVIEW 2 major objections 7 minor 31 references

Minimizing width times depth during AQFP buffer and splitter insertion cuts post-placement area by about 30% versus junction-count minimization.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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2026-07-30 13:24 UTC pith:VCMBBMJV

load-bearing objection Solid AQFP EDA paper: first real W·D legalization objective, fair ~30% placed-area win vs TCAD’25, with one real caveat on how “area” is measured. the 2 major comments →

arxiv 2607.23761 v1 pith:VCMBBMJV submitted 2026-07-26 cs.ET

Bridging AQFP Technology Legalization and Physical Design: Layout-Aware Buffer and Splitter Insertion via Width--Depth Product Minimization

Robert S. Aviles , Ziyu Liu , Madhav Danturthi , Peter A. Beerel This is my paper
classification cs.ET
keywords AQFPsuperconducting logicbuffer and splitter insertiontechnology legalizationwidth-depth productlayout-aware optimizationphysical designNP-complete
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

AQFP superconducting logic needs clocked buffers and splitters after synthesis so every path is balanced and fanouts stay legal. Earlier tools treated that step as a pure cell-count or depth problem. This paper argues that real die area is set by the product of the widest logic row and the number of rows, because each logic level is forced into its own physical row sharing one clock phase. It therefore redefines legalization as minimizing that width–depth product, proves the decision version is NP-complete, and supplies scalable heuristics that move gates, rebuild splitter trees, and selectively stretch depth. On standard benchmarks the new objective yields roughly 30% smaller placed area than the best prior legalizer while adding only about 3% Josephson junctions after placement, showing that a layout-aware proxy at legalization already steers the whole flow toward cheaper chips.

Core claim

The true physical cost of an AQFP circuit after legalization is governed by the product of maximum row width and circuit depth, not by total junction count. Optimizing buffer and splitter insertion directly for that product, rather than for minimum cells, produces legalized netlists whose post-placement area is on average 30% smaller (up to 61% on individual circuits) while the final junction overhead stays near 3%.

What carries the argument

The width–depth product objective together with a matrix formulation that evaluates every legal one-row gate move: local impact vectors for each gate are multiplied by a critical-transitive-closure matrix so the global change in the row-width vector (including implicit path-balancing buffers) is obtained in one sparse multiply, then ranked by the lexicographic score 〈W, |P|, ρ〉.

Load-bearing premise

That under the usual AQFP rule of one dedicated placement row per logic level, maximum row width times depth is a faithful enough proxy for final die area that optimizing it at legalization will systematically beat cell-count legalization on real placed chips.

What would settle it

Take the same logical netlists, legalize them once with the width–depth heuristics and once with a pure junction minimizer, place both with the identical row-based placer and cell library, and check whether the width–depth versions still show a clear average area reduction; if the area gap disappears or reverses, the proxy claim fails.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • AQFP legalizers should report and optimize width–depth product, not only junction count or logic depth.
  • Modest depth increases that relieve peak-row congestion can shrink final area even when they raise cell count.
  • Placement-aware objectives at the legalization stage already reduce the extra buffer rows that placers later insert for interconnect length.
  • The same matrix-move framework can be reused inside joint synthesis-plus-legalization loops that keep layout cost in view from the start.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Other row-structured superconducting families (e.g., RSFQ) that assign clock phases to physical rows may benefit from an analogous width–depth legalization objective.
  • If future placers relax the strict one-level-per-row rule, the numerical value of the proxy will change and the heuristics will need re-tuning, but the principle of feeding layout cost back into legalization remains useful.
  • The observed 30% area win with only 3% junction overhead suggests energy and cooling budgets are almost unaffected while chip cost drops, which matters for in-fridge quantum-control electronics.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 7 minor

Summary. The manuscript reformulates AQFP buffer/splitter insertion (technology legalization) as minimization of the circuit width–depth product W·D, arguing that because AQFP placement constrains each logic level to a dedicated row, maximum row width times depth is a better proxy for physical area than the JJ count minimized by prior work. The authors prove the resulting decision problem NP-complete (reduction from minimum-machine scheduling; membership via a polynomial-size certificate argument), and develop a heuristic flow: minimum-depth splitter-tree initialization from ASAP/ALAP/LP schedules, exact decomposition of candidate gate-move impacts into local impact vectors summed over a critical transitive closure via sparse matrix multiplication, a lexicographic move score ⟨W, |P|, ρ⟩ with a peak-centered critical-density term, and heuristic depth exploration via empty-row insertion. Experiments against the TCAD'25 legalizer of Lee et al. [10] — starting from identical logical netlists and using an identical placer [19] — report an average 28% post-synthesis W·D reduction, 30% post-placement area reduction, and 3% post-placement JJ overhead, with runtime scalability demonstrated to ~48k-gate EPFL benchmarks and one RTL-to-GDSII validation (adder8) closing timing at 5 GHz.

Significance. If the results hold, this is a useful and well-executed contribution to AQFP EDA: it identifies a mismatch between the prevailing legalization objective (JJ count) and the actual structure of AQFP placement cost, and shows that a better-aligned objective yields large area gains at negligible energy cost. The paper ships several things I weight positively: (i) an explicit, checkable NP-completeness proof rather than a complexity claim by assertion; (ii) a reproducible experimental protocol — the comparison starts from the baseline's publicly released legalized netlists with buffers/splitters stripped, uses an identical cell library and placer for both arms, and the authors release their own legalized netlists [29]; (iii) falsifiable ablations (Fig. 9–11) isolating the cost-function components, depth-exploration heuristic, and ω_max sensitivity; (iv) runtime evidence at >46× the scale of the largest fabricated AQFP circuits; and (v) an end-to-end qPALACE RTL-to-GDSII run with Verilog and JoSIM verification and 5 GHz timing closure. The adder8 GDSII result is particularly encouraging: the die-area ratio (5.2/8.6 = 0.605) almost exactly matches the placer-estimate ratio (2.22/3.68 = 0.

major comments (2)
  1. [§V-B Table III vs. §V-D Fig. 8] The headline claim — '30% reduction in post-placement area' — rests on Table III, but the manuscript never defines how the 'Area (mm²)' column is computed. The numbers indicate it is the internal area estimate of the row-based placer [19], not routed die area: for adder8, Table III reports 3.68 mm² (baseline) while §V-D reports a 2 mm × 4.3 mm = 8.6 mm² GDSII die for the same netlist. Because the [19] placer assigns one logic level per row, its area estimate has essentially the functional form (max row width + overhead) × (row count × pitch) — nearly the same form as the W·D objective being optimized. The validation is therefore partly self-confirming: minimizing the proxy minimizes the reported metric close to by construction. The genuinely independent quantity (routed die area) appears only for adder8, where, to the authors' credit, the ratio matches almost exactly (0.605 vs 0.603). Th
  2. [§V, experimental setup] All post-placement evidence is generated with a single placement stack (the [19] placer lineage, one logic level per row) and a single cell library (Table I). The paper's motivating premise — that W·D captures physical cost — is a property of this row-based methodology; under a placer that relaxes the one-level-per-row constraint or uses different interconnect limits, the 30% figure could shrink or vanish. This does not make the result wrong, and the row-based flow is the current community standard, but the abstract and conclusions state the improvement unconditionally ('demonstrating the effectiveness of the proposed objective in reducing true design cost'). The claims should be scoped to the assumed physical methodology, and the discussion should state explicitly what property of the placer the result depends on (per-level rows + interconnect-length-driven buffer-row insertion), ideall
minor comments (7)
  1. [Algorithm 1, line 36] Line 36 sets δ ← δ + 1 upon finding an improving depth, while the loop guard (line 7) is i ≤ δ. As written this extends the patience budget rather than resetting the non-improvement counter i; presumably the intent is i ← 0 (or an equivalent reset). Please clarify, since the termination behavior of depth exploration depends on it.
  2. [§IV-B, Eqs. (12)–(13)] Rows are indexed r ∈ {0, …, D−1}, but Eq. (13) assigns +∞ when r_i = D; this should presumably be r_i = D − 1 (a downstream move from the last row is infeasible). Similarly check the boundary case in Eq. (12).
  3. [§III-B, Theorem 1] The hardness reduction restricts the cell library (unlimited fanout, zero-width buffers). This is legitimate only because the library parameters (s_i, C(i)) are part of the problem input; please state this explicitly, since a reader could otherwise read the formulation as defined for the fixed library of Table I. A one-sentence remark that the problem is parameterized by the library would suffice.
  4. [§V-E] The ablation studies vary ω_max (Fig. 11) but not σ or δω, which are fixed at 60% and 2 throughout. Given that the robustness to ω_max is a selling point, a brief statement (even without a figure) on sensitivity to σ and δω would complete the picture.
  5. [Fig. 1 caption] Typo: 'Row widths ofc3540' → 'Row widths of c3540'.
  6. [Abstract / §IV] Grammar: 'we develop scalable heuristics that integrates legalization' → 'integrate'. Also 'MinArea' in Algorithm 1 line 3 is described in the text (§IV-A) as selecting the minimum-width schedule; please align the naming.
  7. [§V-B] The statement that the 28% post-synthesis W·D reduction 'closely predicts' the 30% area reduction would be more convincing as a per-circuit correlation (e.g., scatter of W·D ratio vs. area ratio across the 21 benchmarks) rather than a comparison of two averages, which could mask divergent per-circuit behavior.

Circularity Check

1 steps flagged

No load-bearing circular derivation; mild proxy–metric coupling under row-based placement is intentional engineering, not a forced identity.

specific steps
  1. other [§III-A Eqs. (1)–(2); §V-B Table III; also §II Fig. 3 and [19]]
    "min W · D s.t. W = max_r (∑_{i∈V: r_i=r} C(i)); "AQFP layouts are constrained to place each logic level in its own physical row"; "average post-synthesis reduction in width–depth product of 28% closely predicts the measured average post-placement area reduction of 30%""

    Not a true circular derivation: the paper openly defines the legalization objective as W·D because the assumed physical methodology assigns one logic level per row, so area is governed by max row width times depth. Table III’s “Area” is then produced by that same row-based placer lineage. Improving the proxy therefore tends to improve the reported metric by shared structure—an intentional, technology-motivated coupling—rather than a hidden fit or self-definition that forces the 30% headline independent of the competing legalizer. Relative gains still require beating TCAD’25 netlists under identical placement; placement-inserted rows and the adder8 GDSII die keep residual independent content. Flagged only as mild proxy–metric alignment.

full rationale

This is an EDA optimization paper, not a first-principles prediction chain. The central empirical claim (≈30% post-placement area cut vs TCAD’25) is established by taking externally released legalized netlists from Lee et al., stripping buffers/splitters, re-legalizing under a W·D objective, and running both through the same external placer [19] and (for adder8) full qPALACE GDSII. The NP-completeness proof reduces from Finke et al.’s minimum-machine scheduling—an independent classical result—not from author self-citation. Hyperparameters (ω_max, δω, σ) only rank moves inside a search; they are not fitted to the reported area ratio and are ablated. Self-citations ([18],[24],[26],[29]) supply tooling/context, not the uniqueness or truth of the area result. The only mild coupling is that AQFP row-based placement makes die area structurally similar to max-row-width × depth—the quantity optimized—so the proxy and the Table III metric share functional form by the technology model the paper explicitly adopts. That is motivated proxy design plus same-stack A/B comparison, not ‘X defined as Y then predicted as Y.’ Placement still inserts extra buffer rows for interconnect limits, changes depth/JJ differently across methods, and the single GDSII die (Fig. 8) independently corroborates the ratio. Score 1 for that residual proxy–evaluator alignment; no step reduces a claimed derivation to its inputs by construction.

Axiom & Free-Parameter Ledger

5 free parameters · 5 axioms · 2 invented entities

The empirical claim rests on standard AQFP timing/fanout rules, the row-per-level physical model from prior placement work, a small set of hand-chosen scoring hyperparameters, and heuristic completeness assumptions—not on new physical entities. Complexity results additionally assume a simplified library (infinite fanout, zero-width buffers) only inside the reduction.

free parameters (5)
  • ω_max (peak-row weight) = 20
    Hand-set maximum weight in the critical-density metric; ablation Fig. 11 shows limited average sensitivity but affects large designs such as alu32.
  • δω (per-row weight decay) = 2
    Linear decay of congestion weights away from each peak row; chosen with ω_max rather than derived.
  • σ (critical threshold fraction) = 60%
    Places τ between ideal average width and current max width; controls which rows enter the density penalty.
  • δ (non-improving depth expansions before stop) = user/algorithm parameter (not numerically fixed in text beyond role)
    Search cutoff for outer depth-exploration loop; affects how far D may grow beyond minimum depth.
  • D_max (maximum allowable circuit depth) = user-specified
    Designer-facing bound on latency vs area tradeoff; expands feasible row assignments.
axioms (5)
  • domain assumption AQFP requires explicit clocked splitters for fanout and path-balancing buffers so every gate input arrives after the same number of clocked stages.
    Stated in Introduction and Background; defines legalization feasibility constraints (Eqs. 6–7).
  • domain assumption Physical AQFP layout assigns each logic level to a dedicated placement row sharing an AC clock phase; area is dominated by max row width times row count.
    Core layout model from §I–III and Figs. 1,3 citing [19],[20]; load-bearing for treating W·D as the objective.
  • standard math Minimum Machine Scheduling is NP-complete (Finke et al.), and the constructed AQFP instance with unit-width gates, unlimited fanout, and zero-width buffers preserves yes/no answers.
    Theorem 1 hardness direction in §III-B.
  • ad hoc to paper Path-balancing buffer width contributions can be encoded in local gate impact vectors so summing over the critical transitive closure equals global W change without re-legalizing the graph.
    §IV-B and Fig. 5; correctness of the matrix move evaluator depends on this composition property.
  • domain assumption The same cell library (Table I) and placement methodology [19] used for both baseline and proposed netlists make post-placement area differences attributable to legalization.
    Experimental protocol in §V; required for the 30% area claim.
invented entities (2)
  • Critical density metric ρ with peak-centered weights ω_p and threshold τ no independent evidence
    purpose: Break ties among moves with equal max width by penalizing congestion clusters around peak rows.
    Defined in §IV-C Eqs. 20–25; internal search heuristic without independent physical existence claims.
  • Critical transitive closure (CTC) matrix move-impact formulation no independent evidence
    purpose: Evaluate all upstream/downstream gate moves via sparse matrix products without repeated graph edits.
    §IV-B Eqs. 12–19; algorithmic device, not a physical postulate.

pith-pipeline@v1.2.0-grok45-kimik3 · 22593 in / 3670 out tokens · 75612 ms · 2026-07-30T13:24:08.539634+00:00 · methodology

0 comments
read the original abstract

Adiabatic Quantum Flux Parametron (AQFP) is an emerging superconducting technology that enables ultra-low energy dissipation approaching the Shannon limit. However, its gate-level pipelining and explicit fanout constraints require technology legalization through buffer and splitter insertion to ensure path balancing and signal distribution, becoming a critical and costly step in the design flow. Prior work has focused on minimizing inserted cell count and logic depth, yet these objectives do not accurately capture the final physical design cost, which is fundamentally governed by the product of circuit width and depth. In this article, we redefine AQFP buffer and splitter insertion optimization as minimizing the circuit width--depth product, a layout-aware metric that more accurately captures physical design area than prior cell minimization efforts. We are the first to formulate buffer and splitter insertion under this objective and prove that the resulting problem is NP-complete. To address this complexity, we develop scalable heuristics that integrates legalization with this objective. Experimental results on standard benchmarks demonstrate that our approach achieves an average 30% reduction in post-placement area compared to state-of-the-art methods, with only a 3% increase in junction count, and on individual circuits up to 61% area reduction, demonstrating the effectiveness of the proposed objective in reducing true design cost.

Figures

Figures reproduced from arXiv: 2607.23761 by Madhav Danturthi, Peter A. Beerel, Robert S. Aviles, Ziyu Liu.

Figure 1
Figure 1. Figure 1: Row widths of c3540, our layout-aware approach significantly reduces maximum row width. Despite these advantages, AQFP imposes unique architec￾tural and timing constraints that complicate large-scale design and require specialized electronic design automation (EDA) support [9]. In particular, all AQFP gates are clocked, and signals with fanout greater than one must be driven by explicit clocked splitter ga… view at source ↗
Figure 2
Figure 2. Figure 2: Circuit Construction of AQFP Buffer. Current directions shown [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: AQFP placement constrains each logic level to be assigned to [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Layout-Aware top-level flow Gate move selection must account for the impact of all affected Transitive Fanin/Fanout (TFI/TFO) gates as well as any buffers required to maintain legality. Explicitly inserting and removing these buffers after every candidate move would repeatedly modify the graph representation, substantially in￾creasing both graph size and move evaluation cost. Instead, the proposed framewor… view at source ↗
Figure 5
Figure 5. Figure 5: Decomposition of a downstream gate move ( [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Matrix formulation for candidate move evaluation. Local gate impacts are accumulated across the critical transitive closure through [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Illustration of the proposed critical density metric. Row contributions are computed relative to the critical threshold [PITH_FULL_IMAGE:figures/full_fig_p008_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: presents the resulting GDSII layouts for adder8 generated using the proposed layout-aware legalization and the JJ-minimization legalization of [10]. The layouts visually illustrate the motivation behind the proposed optimization. The JJ-minimized design exhibits a highly concentrated placement row that determines the overall die width, increasing total area despite the downstream logic remaining sparsely p… view at source ↗
Figure 9
Figure 9. Figure 9: Comparison of layout-aware results using a cost function of just [PITH_FULL_IMAGE:figures/full_fig_p012_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Ablation evaluating impact of the location where the empty [PITH_FULL_IMAGE:figures/full_fig_p012_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Ablation studying the impact of the chosen maximum weight [PITH_FULL_IMAGE:figures/full_fig_p012_11.png] view at source ↗

discussion (0)

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Reference graph

Works this paper leans on

31 extracted references · 1 linked inside Pith

  1. [1]

    An adiabatic quantum flux parametron as an ultra-low-power logic device,

    N. Takeuchi, D. Ozawa, Y . Yamanashi, and N. Yoshikawa, “An adiabatic quantum flux parametron as an ultra-low-power logic device,”Supercon- ductor Science and Technology, vol. 26, no. 3, p. 035010, jan 2013

    2013

  2. [2]

    Adiabatic quantum-flux-parametron: Towards building extremely energy-efficient circuits and systems,

    O. Chen, R. Cai, Y . Wang, F. Ke, T. Yamae, R. Saito, N. Takeuchi, and N. Yoshikawa, “Adiabatic quantum-flux-parametron: Towards building extremely energy-efficient circuits and systems,”Scientific reports, vol. 9, no. 1, p. 10514, 2019

    2019

  3. [3]

    Microwave-multiplexed qubit controller using adiabatic superconductor logic,

    N. Takeuchi, T. Yamae, T. Yamashita, T. Yamamoto, and N. Yoshikawa, “Microwave-multiplexed qubit controller using adiabatic superconductor logic,”npj Quantum Information, vol. 10, no. 1, p. 53, 2024

    2024

  4. [4]

    QECOOL: On-line quantum error correction with a superconducting decoder for surface code,

    Y . Ueno, M. Kondo, M. Tanaka, Y . Suzuki, and Y . Tabuchi, “QECOOL: On-line quantum error correction with a superconducting decoder for surface code,” in2021 58th ACM/IEEE DAC. IEEE, dec 2021

    2021

  5. [5]

    A streaming architecture for quantum error syndrome compression at 4 kelvin,

    P. Papanikolaou, R. Hou, J. V olk, and G. Tzimpragos, “A streaming architecture for quantum error syndrome compression at 4 kelvin,” in Proceedings of the 53rd Annual International Symposium on Computer Architecture (ISCA). Association for Computing Machinery, 2026

    2026

  6. [6]

    Design and im- plementation of energy-efficient binary neural networks using adiabatic quantum-flux-parametron logic,

    T. Yamauchi, H. San, N. Yoshikawa, and O. Chen, “Design and im- plementation of energy-efficient binary neural networks using adiabatic quantum-flux-parametron logic,”IEEE Transactions on Applied Super- conductivity, vol. 33, no. 5, pp. 1–5, 2023

    2023

  7. [7]

    MANA: A monolithic adiabatic integration architec- ture microprocessor using 1.4-zJ/op unshunted superconductor josephson junction devices,

    C. L. Ayala, T. Tanaka, R. Saito, M. Nozoe, N. Takeuchi, and N. Yoshikawa, “MANA: A monolithic adiabatic integration architec- ture microprocessor using 1.4-zJ/op unshunted superconductor josephson junction devices,”IEEE Journal of Solid-State Circuits, vol. 56, no. 4, pp. 1152–1165, 2021

    2021

  8. [8]

    SCE-NTT: A hardware accelerator for number theoretic transform using superconductor electronics,

    S. Razmkhah, M. Li, Z. Cheng, R. S. Aviles, K. Jackman, J. Delport, L. Schindler, W. Luo, T. Suzuki, M. Kamal, C. L. Ayala, C. J. Fourie, N. Yoshikawa, P. A. Beerel, S. Gupta, and M. Pedram, “SCE-NTT: A hardware accelerator for number theoretic transform using superconductor electronics,” 2025. [Online]. Available: https://arxiv.org/abs/2508.21265

    Pith/arXiv arXiv 2025

  9. [9]

    Challenges and unexplored frontiers in electronic design automation for superconducting digital logic,

    S. Razmkhah, R. S. Aviles, M. Li, S. Gupta, P. A. Beerel, and M. Pedram, “Challenges and unexplored frontiers in electronic design automation for superconducting digital logic,” in2024 DATE, 2024, pp. 1–6

    2024

  10. [10]

    Technology legalization and optimization for adiabatic quantum-flux parametron,

    S.-Y . Lee, A. Tempia Calvino, H. Riener, and G. De Micheli, “Technology legalization and optimization for adiabatic quantum-flux parametron,” IEEE TCAD-ICS, vol. 44, no. 1, pp. 186–199, 2025

    2025

  11. [11]

    Buffer and splitter insertion for adiabatic quantum-flux-parametron circuits,

    R. Fu, M. Wang, Y . Kan, O. Chen, N. Yoshikawa, B. Yu, and T.-Y . Ho, “Buffer and splitter insertion for adiabatic quantum-flux-parametron circuits,”IEEE TCAD-ICS, vol. 44, no. 3, pp. 975–988, 2025

    2025

  12. [12]

    A buffer and splitter insertion framework for adiabatic quantum-flux-parametron superconducting circuits,

    R. Cai, O. Chen, A. Ren, N. Liu, N. Yoshikawa, and Y . Wang, “A buffer and splitter insertion framework for adiabatic quantum-flux-parametron superconducting circuits,” in2019 IEEE (ICCD), 2019, pp. 429–436

    2019

  13. [13]

    Depth-optimal buffer and splitter insertion and optimization in AQFP circuits,

    A. T. Calvino and G. De Micheli, “Depth-optimal buffer and splitter insertion and optimization in AQFP circuits,” in2023 28th ASP-DAC, 2023, pp. 152–158

    2023

  14. [14]

    Beyond local optimality of buffer and splitter insertion for AQFP circuits,

    S.-Y . Lee, H. Riener, and G. De Micheli, “Beyond local optimality of buffer and splitter insertion for AQFP circuits,” in59th DAC 2022. New York, NY , USA: ACM, 2022, p. 445–450

    2022

  15. [15]

    A global optimization algorithm for buffer and splitter insertion in adiabatic quantum-flux-parametron circuits,

    R. Fu, M. Wang, Y . Kan, N. Yoshikawa, T.-Y . Ho, and O. Chen, “A global optimization algorithm for buffer and splitter insertion in adiabatic quantum-flux-parametron circuits,” in2023 28th ASP-DAC, 2023, pp. 769–774

    2023

  16. [16]

    An optimal algorithm for splitter and buffer insertion in adiabatic quantum-flux- parametron circuits,

    C.-Y . Huang, Y .-C. Chang, M.-J. Tsai, and T.-Y . Ho, “An optimal algorithm for splitter and buffer insertion in adiabatic quantum-flux- parametron circuits,” in2021 ICCAD, 2021, pp. 1–8

    2021

  17. [17]

    An efficient and effective optimization algorithm for buffer and splitter insertion in AQFP circuits,

    B.-H. Wu and W.-K. Mak, “An efficient and effective optimization algorithm for buffer and splitter insertion in AQFP circuits,”ACM Trans. Des. Autom. Electron. Syst., vol. 31, no. 3, Feb. 2026

    2026

  18. [18]

    A joint optimization of buffer and splitter insertion for phase-skipping adiabatic quantum-flux-parametron circuits,

    R. S. Aviles and P. A. Beerel, “A joint optimization of buffer and splitter insertion for phase-skipping adiabatic quantum-flux-parametron circuits,” in2024 IEEE 42nd International Conference on Computer Design (ICCD), 2024, pp. 534–541

    2024

  19. [19]

    Towards AQFP-capable physical design automation,

    H. Li, M. Sun, T. Zhang, O. Chen, N. Yoshikawa, B. Yu, Y . Wang, and Y . Lin, “Towards AQFP-capable physical design automation,” in2021 DATE, 2021, pp. 954–959

    2021

  20. [20]

    Standard cell layout synthesis for row-based placement and routing of RSFQ and AQFP logic families,

    L. Schindler, R. van Staden, C. J. Fourie, C. L. Ayala, J. A. Coetzee, T. Tanaka, R. Saito, and N. Yoshikawa, “Standard cell layout synthesis for row-based placement and routing of RSFQ and AQFP logic families,” in 2019 IEEE International Superconductive Electronics Conference (ISEC), 2019, pp. 1–5

    2019

  21. [21]

    In-depth timing charac- terization of the adiabatic quantum-flux-parametron logic gate,

    Y . Hoshika, C. L. Ayala, and N. Yoshikawa, “In-depth timing charac- terization of the adiabatic quantum-flux-parametron logic gate,”IEEE Transactions on Applied Superconductivity, vol. 34, no. 4, pp. 1–8, 2024

    2024

  22. [22]

    Adiabatic quantum-flux- parametron cell library adopting minimalist design,

    N. Takeuchi, Y . Yamanashi, and N. Yoshikawa, “Adiabatic quantum-flux- parametron cell library adopting minimalist design,”Journal of Applied Physics, vol. 117, no. 17, p. 173912, 05 2015

    2015

  23. [23]

    Three-input gates for logic synthesis,

    D. S. Marakkalage, E. Testa, H. Riener, A. Mishchenko, M. Soeken, and G. De Micheli, “Three-input gates for logic synthesis,”IEEE TCAD-ICS, vol. 40, no. 10, pp. 2184–2188, 2021

    2021

  24. [24]

    qPRO-AQFP: Post-routing optimization of AQFP circuits with delay line clocking,

    R. S. Aviles, Z. Liu, J. Hong, S. Razmkhah, M. Pedram, and P. A. Beerel, “qPRO-AQFP: Post-routing optimization of AQFP circuits with delay line clocking,” inProceedings ISVLSI, 2026

    2026

  25. [25]

    Minimizing the number of machines for minimum length schedules,

    G. Finke, P. Lemaire, J.-M. Proth, and M. Queyranne, “Minimizing the number of machines for minimum length schedules,”European Journal of Operational Research, vol. 199, no. 3, pp. 702–705, 2009

    2009

  26. [26]

    An efficient and scalable clocking assignment algorithm for multi-threaded multi-phase single flux quantum circuits,

    R. S. Aviles, X. Li, L. Lu, Z. Ni, and P. A. Beerel, “An efficient and scalable clocking assignment algorithm for multi-threaded multi-phase single flux quantum circuits,” in2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2024, pp. 266–271

    2024

  27. [27]

    Sensitivity guided net weighting for placement-driven synthesis,

    H. Ren, D. Pan, and D. Kung, “Sensitivity guided net weighting for placement-driven synthesis,”IEEE TCAD-ICS, vol. 24, no. 5, pp. 711– 721, 2005

    2005

  28. [28]

    DREAMPlace 4.0: Timing-driven placement with momentum-based net weighting and lagrangian-based refinement,

    P. Liao, D. Guo, Z. Guo, S. Liu, Y . Lin, and B. Yu, “DREAMPlace 4.0: Timing-driven placement with momentum-based net weighting and lagrangian-based refinement,”IEEE TCAD-ICS, vol. 42, no. 10, pp. 3374– 3387, 2023

    2023

  29. [29]

    Layout-aware AQFP optimizations,

    R. S. Aviles, “Layout-aware AQFP optimizations,” https://github.com/robertsaviles/Layout-Aware-AQFP-Optimizations, 2026, open-source repository. 14

    2026

  30. [30]

    Demonstration of 10k gate-scale adiabatic-quantum-flux-parametron cir- cuits,

    T. Narama, Y . Yamanashi, N. Takeuchi, T. Ortlepp, and N. Yoshikawa, “Demonstration of 10k gate-scale adiabatic-quantum-flux-parametron cir- cuits,” in2015 15th International Superconductive Electronics Conference (ISEC), 2015, pp. 1–3

    2015

  31. [31]

    qPALACE: A suite of EDA tools for synthesis and physical design optimization of single flux quantum logic circuits,

    M. Pedram, “qPALACE: A suite of EDA tools for synthesis and physical design optimization of single flux quantum logic circuits,”Proc. 33rd Int. Symp. Supercond., 2020

    2020