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REVIEW 2 major objections 3 minor 39 references

MC3: Memory Contention based Covert Channel Communication on Shared DRAM System-on-Chips

T0 review · 2 major / 3 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read A software-only covert channel exploits shared DRAM on mobile SoCs, reaching 6.4 kbps without a shared cache or elevated privileges.

desk verdict Real CPU-to-GPU DRAM-contention channel on mobile SoCs, but the headline '6.4 kbps at <1% error' contradicts the paper's own Figure 9 and needs an honest rewrite. read the letter →

arxiv 2412.05228 v2 pith:VY2UK5OI submitted 2024-12-06 cs.CR

Ismet Dagli , James Crea , Soner Seckiner , Yuanchao Xu , Selçuk Köse , Mehmet E. Belviranli This is my paper · ORCID
classification cs.CR
keywords covertchannelsharedmemorySoCDRAMcontentionnon-temporalloadsArm64ldnp/stnpCPU-GPUcommunicationcontrollermobilesecurity
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that on mobile system-on-chips where the CPU and GPU share DRAM but have no shared last-level cache, two unprivileged applications can still build a high-throughput covert channel. The transmitter creates memory pressure by repeatedly copying a buffer with non-temporal Arm64 instructions ($ldnp$/$stnp$) that bypass private caches and hit DRAM directly, while the receiver measures its own copy bandwidth and reads bits from the resulting dips. The authors report rates up to 6.4 kbps with under 1% error on three NVIDIA Orin boards, and near-perfect accuracy when the rate is lowered. A sympathetic reader should care because the result shows the shared DRAM itself, not a shared cache, can serve as a leakage medium on mobile and autonomous SoCs.

What carries the argument

The central mechanism is a DRAM-contention kernel built on non-temporal load/store pair ($ldnp$/$stnp$) Arm64 instructions, which are supposed to bypass the private cache hierarchy and generate direct memory-controller pressure. The transmitter modulates this pressure by toggling between contention and sleep over a fixed interval $T$; the receiver observes its own copy bandwidth and decodes with running-average normalization plus hysteresis thresholding. The capacity equation $1 / (Time_{T_x} \times Slowdown_{R_x})$ captures the inverse trade-off between transmitter buffer size and channel rate, while the receiver-to-transmitter copy-epoch ratio ($R/T$) is the knob that trades throughput for noise resistance.

What would settle it

Run the MC3 transmitter-receiver pair on an Orin-class board while a third workload continuously streams DRAM at 30-50% of peak bandwidth; if the bit-error rate at 6.4 kbps rises well above 1% or the high/low bandwidth distributions overlap, the claim that the channel holds under multi-application conditions is refuted. Separately, a microbenchmark with hardware performance counters can check whether $ldnp$/$stnp$ actually miss all cache levels; if those loads hit L1 or L2 on the target CPU, the cache-bypass premise fails and the contention kernel is not actually DRAM-direct.

Watch

Extended reading notes

Core claim

MC3 is a software-only covert channel that encodes bits in memory-contention on the shared physical DRAM of mobile SoCs. To send '0' the transmitter sleeps for a fixed interval; to send '1' it runs a buffer-copy contention kernel. The receiver continuously copies its own buffer, normalizes its measured bandwidth against a running global average, and applies a hysteresis threshold to decode '0' and '1'. Because the contention kernel uses non-temporal $ldnp$/$stnp$ load/store pair instructions, the accesses are meant to bypass the private cache hierarchy and reach the memory controller, making the slowdown observable even when the transmitter is on the CPU and the receiver on the GPU. On NVIDIA Orin AGX, Orin NX, and Orin Nano, the paper reports up to 6.4 kbps channel capacity with error below 1%, and 99.99% accuracy when the capacity is capped at about 1.3 kbps.

Load-bearing premise

The channel stands on two premises: non-temporal $ldnp$/$stnp$ loads truly bypass the private cache hierarchy on the target CPUs, and the memory controller's arbitration turns the transmitter's copy traffic into a repeatable, microsecond-observable bandwidth dip at the receiver even when other applications are using DRAM; the paper validates the first on Orin hardware but only asserts, without measurement, that third-party memory traffic is handled by a history-based heuristic.

Editorial extensions

If this is right

  • Unprivileged applications on shared-DRAM mobile SoCs can exfiltrate data across CPU-GPU boundaries without any shared cache or special permissions.
  • The R/T epoch ratio gives an operator a direct dial between speed and reliability, so the same channel can be tuned for fast bulk transfer or near-error-free short messages.
  • Memory-controller scheduling policies on SoCs without a shared LLC become a security-relevant decision, since a predictable arbitration creates the observable bandwidth dips.
  • The technique works on at least three Orin-family devices with different memory bandwidths, suggesting the mechanism generalizes across that hardware generation.
  • Because the transmitter only sleeps or copies memory, the attack avoids performance counters, privileged APIs, and physical access, making remote deployment plausible.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the same arbitration behavior appears on other shared-memory SoCs (Apple M-series, Qualcomm Snapdragon), the attack likely transfers, but the reported bit rates are only measured on Orin hardware and should not be assumed elsewhere.
  • A concrete countermeasure would be to randomize or spread memory-controller scheduling so that transmitter-induced pressure no longer yields a stable bandwidth dip; the paper does not evaluate such defenses.
  • The channel's robustness under concurrent third-party memory traffic is asserted with a heuristic but not measured, so the error-rate figures are probably optimistic for busy real-world devices.
  • Future Arm implementations that prefetch or partially cache non-temporal loads would directly weaken the cache-bypass assumption, making the channel's reliability a moving target across silicon revisions.
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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 3 minor

Summary. The manuscript introduces MC3, a software-only covert channel that encodes bits by modulating DRAM contention between a transmitter and a receiver on NVIDIA Orin SoCs. The transmitter uses non-temporal Arm64 load/store instructions to generate memory pressure that is observable as a bandwidth drop at the receiver, with no shared LLC, no elevated privileges, and no physical access. The paper evaluates CPU-to-GPU and CPU-to-CPU configurations on Orin AGX, NX, and Nano, and reports a trade-off between channel capacity and transmission accuracy. The headline claim is that MC3 achieves up to 6.4 kbps with less than 1% error rate.

Significance. If the reported measurements are reliable, MC3 demonstrates a new practical attack surface on shared-memory mobile SoCs: unprivileged, software-only, high-throughput communication through DRAM contention, without relying on an LLC. The paper's strengths include the use of raw traces, systematic parameter sweeps over transmitter and receiver buffer sizes, evaluation on three real platforms, and a publicly available implementation. The main technical risk is not circularity, since the channel is measured empirically, but rather an internal inconsistency in the headline rate/error claim and a lack of validation under concurrent third-party memory traffic.

major comments (2)
  1. [Abstract, Section I, Section VI-D, Fig. 9a] The abstract and Section I state that MC3 achieves 'up to 6.4 kbps with less than 1% error rate.' This is contradicted by Section VI-D and Fig. 9a, which report that at the maximum per-interval copy count with a 1 MB transmitter buffer the channel capacity is approximately 6.4 kbps with 94.9% accuracy, i.e., a 5.1% error rate. The 99.99% accuracy point occurs at 1.3 kbps, and 99.1% accuracy at 3.5 kbps. The contributions bullet in Section I already states the trade-off correctly ('up to 6.4 Kbps with 95% accuracy' and '99.99% when the capacity is capped at 1.3 Kbps'). The abstract and introduction should be revised to present this either/or trade-off; as written, the strongest claim is internally inconsistent with the paper's own evaluation.
  2. [Section I, Section V-A] The paper claims in Section I that the attack works in 'single-user and multi-application environments.' The only support is one sentence in Section V-A stating that other applications' memory usage can be handled with 'heuristic history-based signal processing approaches.' No experiment introduces concurrent third-party memory traffic, so the multi-application claim is not supported by the presented evidence. The authors should either add an experiment with a background memory load or qualify the claim to quiet, single-application environments.
minor comments (3)
  1. [Section V-C] The claim that ldnp/stnp non-temporal instructions bypass all cache levels is essential to the mechanism but is supported only by a citation to the Arm architecture manual. A short microbenchmark on the target Orin platforms comparing achieved DRAM bandwidth with and without non-temporal hints would make this assumption more convincing.
  2. [Section VI-D, Fig. 9, Abstract] The paper switches between 'accuracy' and 'error rate' without consistently stating the conversion. Since the abstract promises 'less than 1% error rate,' please state explicitly that accuracy = 100% - error rate and use one convention throughout.
  3. [Section VI-B] The statement that GPU-based receivers achieve 2x-4x higher channel capacities on Orin Nano than CPU-based receivers is not supported by a displayed result; the accompanying figure (Fig. 7) shows only Orin AGX data. Please either include the Orin Nano data or mark this as an observed trend without a supporting figure.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: MC3's channel results are measured on hardware, not derived from fitted parameters or author self-citations.

full rationale

MC3's central claims are evaluated empirically on Orin hardware. The transmitter and receiver algorithms (Alg. 1 and Alg. 2) encode and decode by modulating and sensing DRAM contention, and no equation in the paper derives bitrate or accuracy from a model that already contains those values. The only tuned parameter, the hysteresis threshold gamma, is a decoding threshold; the reported capacity and accuracy numbers are measured operating points, not predictions forced by construction. Self-citations (Refs. [6], [7], [37]) appear only as background for the well-known observation that shared-memory contention slows concurrent workloads, and Section IV independently demonstrates that effect in Fig. 3, so no load-bearing step reduces to a self-citation. The global-average normalization is a signal-processing step, not a circular argument. I therefore find no significant circularity. I do note two non-circular defects: the abstract's claim of 'up to 6.4 kbps with less than 1% error rate' is inconsistent with Fig. 9a, where the 6.4 kbps operating point has 94.9% accuracy (about 5.1% error), and the noise-robustness claim under concurrent third-party memory traffic is asserted via a heuristic rather than experimentally demonstrated. These are correctness and robustness concerns, not circularity.

Assumptions & free parameters 5 free parameters · 4 assumptions · 0 invented entities

MC3 is an experimental attack paper, not a derivation. The central rate and accuracy numbers depend on several hand-tuned parameters (hysteresis threshold, buffer sizes, epoch ratios) and on hardware behavior assumptions about cache bypass, memory controller arbitration, and user-space timing. No new physical entities are introduced, so the invented entity list is empty.

free parameters (5)
  • Hysteresis threshold gamma = not reported as a number
    Experimentally determined in Alg. 2 and applied to normalized bandwidth; used to classify bits. Accuracy is reported on the same traces that informed gamma, so the operating point may be optimistic.
  • Bit time interval T = varies with buffer size and epoch ratio
    Chosen per experiment; sets symbol rate and synchronization window. It directly sets the capacity in Eq. 1.
  • Transmitter buffer size = 1-2 MB for headline results
    Controls contention strength; Fig. 9 sweeps this parameter and shows larger buffers trade capacity for accuracy.
  • Receiver buffer size = 1-2 MB for headline results
    Controls sensitivity and R/T alignment; Fig. 9 sweeps this parameter and shows imbalance beyond 5 MB.
  • R/T copy epoch ratio = 1 to 10
    Number of receiver copy iterations per transmitted bit; increased to reduce noise at the cost of capacity.
assumptions (4)
  • domain assumption SM-SoCs such as Orin have no shared LLC between CPU and GPU, so system DRAM is the only shared resource and all PU traffic crosses one memory controller.
    Invoked in Section II-A and Fig. 1; if a shared LLC existed, the contention channel would be a cache channel and MC3's premise would change.
  • domain assumption Arm64 ldnp/stnp non-temporal load and store instructions bypass the cache hierarchy and generate DRAM traffic.
    Invoked in Section V-C, relying on the Arm Architecture Reference Manual; if the SoC implements them as ordinary cached accesses, the receiver's bandwidth signal is polluted by cache hits.
  • domain assumption The memory controller's arbitration under contention produces bandwidth reductions large and regular enough to be observed in microsecond-scale copy durations.
    Section IV and Fig. 3 demonstrate this on three Orin boards; generalization to other SoCs is assumed, not proven.
  • domain assumption User-space timing using sleep_for plus a spin loop gives sufficient precision without privileged timers.
    Section V-D; needed for transmitter and receiver synchronization without root access.

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Cite this review

Pith. "Pith review of MC3: Memory Contention based Covert Channel Communication on Shared DRAM System-on-Chips." pith.science (2026). https://pith.science/paper/VY2UK5OI

@misc{pith2026241205228,
  author       = {Pith},
  title        = {Pith review of: MC3: Memory Contention based Covert Channel Communication on Shared DRAM System-on-Chips},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/VY2UK5OI}},
  note         = {Machine review of arXiv:2412.05228}
}
read the original abstract

Shared-memory system-on-chips (SM-SoC) are ubiquitously employed by a wide-range of mobile computing platforms, including edge/IoT devices, autonomous systems and smartphones. In SM-SoCs, system-wide shared physical memory enables a convenient and financially-feasible way to make data accessible by dozens of processing units (PUs), such as CPU cores and domain specific accelerators. In this study, we investigate vulnerabilities that stem from the shared use of physical memory in such systems. Due to the diverse computational characteristics of the PUs they embed, SM-SoCs often do not employ a shared last level cache (LLC). While the literature proposes covert channel attacks for shared memory systems, high-throughput communication is currently possible by either relying on an LLC or privileged/physical access to the shared memory subsystem. In this study, we introduce a new memory-contention based covert communication attack, MC3, which specifically targets the shared system memory in mobile SoCs. Different from existing attacks, our approach achieves high throughput communication between applications running on CPU and GPU without the need for an LLC or elevated access to the system. We extensively explore the effectiveness of our methodology by demonstrating the trade-off between the channel transmission rate and the robustness of the communication. We demonstrate the utility of MC3 on NVIDIA Orin AGX, Orin NX, and Orin Nano up to a transmit rate of 6.4 kbps with less than 1% error rate.

Figures

Figures reproduced from arXiv: 2412.05228 by the authors.

Figure 1
Figure 1. Block diagram for NVIDIA’s Xavier AGX SoC embedding a CPU, GPU, deep learning accelerator (DLA) and shared memory. increase perceived bandwidth, hence, they should be minimized to achieve a reliable access stream reaching the DRAM. This is also crucial to maximize the capacity of the communication channel. (iii) Without external synchronization mechanisms, reliable and high-throughput data transmission over SM becom… view at source ↗
Figure 3
Figure 3. Raw traces for CPU-to-GPU and CPU-to-CPU communication signature can be used to leak crucial information that can be encoded in binary form. Although this attack strategy seems similar to other types of covert channel attacks, there are unique challenges to efficiently and reliably designing shared memory contention channels: • Sufficiently observable contention: While fully stressing memory resources to maximize co… view at source ↗
Figure 4
Figure 4. illustrates the communication protocol between the transmitter and receiver for transmitting bits (i.e., 0 or 1) through shared memory contention. The transmitter conveys bits by performing buffer copy operations on memory while the receiver continuously performs another buffer copy operation to detect the transmitted bit. The transmitter is responsible for sending the bit by modu￾lating the level of memory contenti… view at source ↗
Figures from the paper (4 more)
Figure 5
Figure 5. Figure 5: (a) [Left] Average slowdown in the perceived BW depending on the transmitter buffer size. (b) [Middle] Average perceived high BW (H) and low BW (L) for bits ‘0’ and ‘1’, respectively, for varying receiver buffer sizes. (c) [Right] MC utilization per transmitter buffer …
Figure 6
Figure 6. Figure 6: The overlap between [T]ransmitter’s and [R]eceiver’s copy operations for various R/T copy epoch ratios. ‘Ideal’ represents the expected durations and ‘actual’ represents the observed. R1-R5 indi￾cates the epoch number of a copy operation performed by the receiver. resu…
Figure 8
Figure 8. Figure 8: Average BW observed by the receiver while receiving a "Hello, World" message. cudaMemcpy using CUDA [26] [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]
Figure 9
Figure 9. Figure 9: The trade-off between accuracy and channel capacity for varying (a) transmitter [left] and (b) receiver buffer sizes [right]. portion of the message is transmitted and received with 100% accuracy while the entire message is delivered with 99.02% accuracy at a channel c…

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