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OpenGeMM: A High-Utilization GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling

T0 review · 3 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read OpenGeMM is a programmable GeMM generator that reports 81.89%–99.34% array utilization on real DNN workloads and 3.58–16.40x normalized throughput gains over the baseline system.

desk verdict Useful open-source GeMM accelerator with credible utilization results; the speedup claim needs a fairer baseline and full-system accounting. read the letter →

arxiv 2411.09543 v2 pith:WH7LRBUT submitted 2024-11-14 cs.AR cs.AI

Xiaoling Yi , Ryan Antonio , Joren Dumoulin , Jiacong Sun , Josse Van Delm , Guilherme Paim , Marian Verhelst This is my paper · ORCID
classification cs.ARcs.AI
keywords GeMMacceleratorhardwaregeneratorRISC-Vscratchpadmemoryoutput-stationarydataflowDNNworkloadsedgeAIutilization
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

OpenGeMM is an open-source, configurable hardware platform for matrix-multiplication (GeMM) acceleration aimed at edge DNN inference. The paper tries to establish that a GeMM accelerator can combine programmability with sustained high utilization—not just high peak throughput—by pairing a lightweight RISC-V control core with a tightly coupled multi-banked scratchpad memory and three system-level mechanisms: configuration pre-loading, input pre-fetching with output buffering, and programmable strided memory access. Across MobileNetV2, ResNet18, ViT-B-16, and BERT-Base, the design reports 81.89% to 99.34% overall GeMM core utilization, and 3.58x to 16.40x area-normalized throughput speedups over the open-source baseline generator. The authors also report 4.68 TOPS/W system efficiency at 200 MHz in 16nm. The significance would be that flexible, CPU-programmed DNN accelerators need not sacrifice efficiency or utilization, contrary to the usual trade-off.

What carries the argument

The central object is the 3D MAC array, an $(M_u, N_u)$ mesh of $K_u$-length dot-product units that spatially unrolls all three dimensions of a GeMM tile. Each dot-product unit accumulates a partial sum in an output-stationary register, while A and B vectors are broadcast across rows and columns to maximize data reuse. Around this core, the load-bearing mechanisms are the pre-loadable CSR configuration registers, the producer-consumer pre-fetch buffers, and the strided address generator units (AGUs) that place streams to avoid multi-banked scratchpad contention.

What would settle it

Rerun the OpenGeMM RTL simulations while including all off-chip DRAM-to-SRAM transfer cycles in the execution-time count, and run the baseline generator on the same technology node with the same configuration; if utilization falls below the reported 81.89%–99.34% range or the normalized throughput advantage drops toward 1x, the central claim fails.

Watch

Extended reading notes

Core claim

The central claim is that a GeMM accelerator can be made to run real DNN workloads at near-peak array utilization through careful coupling of a small RISC-V core and a multi-banked scratchpad. Specifically, the paper demonstrates that three mechanisms—configuration pre-loading (overlapping CSR programming with compute), input pre-fetch with output buffering (keeping data in flight so the MAC array never waits), and programmable strided address generation (avoiding scratchpad bank conflicts)—together raise median utilization 2.78x over a baseline version of the same platform. On four full models, the measured overall utilization spans 81.89% (MobileNetV2) to 99.34% (BERT-Base), and the platform achieves 4.68 TOPS/W.

Load-bearing premise

The reported utilization and speedup numbers count only on-chip cycles and use published performance data from a different technology node for the baseline, so if off-chip memory traffic were included in the cycle count or the baseline were run under identical conditions, the headline gains could change.

Editorial extensions

If this is right

  • The same generated 8x8x8 array reaches 96% or higher utilization on ResNet18 and Transformer workloads, meaning one fixed tiling can cover both CNN and Transformer inference without per-model redesign.
  • The ablation study attributes a 2.78x median utilization improvement to the three mechanisms, so the mechanisms transfer to other accelerator generators as a recipe for hiding control and memory latency.
  • Because programming happens through standard RISC-V CSR instructions with a pre-loading scheme, software can switch layer configurations without stalling compute, keeping the core busy across layer boundaries.
  • With a control core occupying roughly 1.13% of system area and 2.4% of power, the result implies that programmability costs little when the memory system is coupled tightly to the array.
  • The reported 4.68 TOPS/W system efficiency and best operation-area efficiency among compared int8 platforms suggest the design is competitive for edge deployment at 200 MHz.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A natural testable extension is to count off-chip DRAM-to-SRAM cycles in the utilization metric; if the reported 81.89%–99.34% holds with those cycles included, OpenGeMM's claim would be even stronger.
  • The strided-address mechanism implies a compiler-level layout optimizer could be built to choose bank-aware strides automatically for arbitrary matrix shapes, extending the work beyond hand-tiled workloads.
  • The same pre-loading and buffering recipe could be applied to other streaming accelerators, such as convolvers or attention engines, where configuration latency and memory stalls are the main utilization limiters.
  • The reported power and area figures come from a single block-matrix workload at one voltage and frequency point; full-model energy measurements would clarify whether the 4.68 TOPS/W figure holds in end-to-end inference.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. OpenGeMM proposes an open-source, parameterized Chisel-based GeMM accelerator generator integrated with a lightweight RISC-V Snitch core and a tightly coupled multi-banked scratchpad memory. Three system-level mechanisms—configuration pre-loading, input prefetching with output buffering, and programmable strided memory access—are introduced to maintain high MAC array utilization. The paper reports cycle-accurate RTL simulation results showing 81.89%–99.34% overall utilization across MobileNetV2, ResNet18, ViT-B-16, and BERT-Base, and claims 3.58×–16.40× normalized throughput speedup over Gemmini as well as 4.68 TOPS/W system efficiency, with area and power breakdowns from TSMC 16nm synthesis.

Significance. If the headline claims hold, OpenGeMM is a valuable open-source contribution: the generator approach, the lightweight control integration, and the three utilization-enhancement mechanisms are well motivated, and the RTL-simulation-based ablation study is a credible methodology for the core utilization claim. The open-source release and the parameterized Chisel generator are concrete strengths that will enable reproduction and extension. However, the headline speedup and system-efficiency numbers depend on the comparison boundary chosen in Footnote 2 and on an external Gemmini baseline; these dependencies need to be made precise and quantified before the central performance comparison can be accepted as stated.

major comments (3)
  1. [Section 4.3, Footnote 2] The footnote states that DRAM-to-SRAM data movement cycles are not counted. Consequently, the utilization and cycle counts in Table 2 are compute-plus-SPM metrics, not end-to-end execution times, while the abstract and Section 4.4 present the 3.58×–16.40× speedup and 4.68 TOPS/W as system-level results without this caveat. This is load-bearing: for edge workloads, off-chip fill time can dominate when the SPM is limited. Please report end-to-end cycles including DMA/DRAM fill, or provide a quantitative sensitivity analysis that shows how the speedup and TOPS/W change under realistic DRAM bandwidth assumptions.
  2. [Table 3 and Figure 7] The Gemmini baseline is taken from [32], a 22nm FinFET SoC running at 1 GHz with 512 GOPS peak, while OpenGeMM is synthesized in TSMC 16nm at 200 MHz. The area-normalized throughput comparison (GOPS/mm^2) therefore mixes process node, frequency, and memory-accounting conventions, and the unqualified 'speedup' wording overstates the comparison. Please either run Gemmini under the same simulation flow and memory-accounting boundary, or clearly label the result as an estimated cross-implementation comparison and remove the unqualified 'speedup' language. Additionally, specify where the 'average temporal utilization on average 6.25%' for Gemmini comes from; if it is taken from [32], give the workloads and Gemmini configuration used.
  3. [Section 4.4] The 4.68 TOPS/W efficiency is computed from a total power of 43.8 mW, but the power breakdown in Figure 6 appears to include only on-chip components (SPM, GeMM core, instruction cache, streamers). If DRAM access power is excluded, the metric should be labeled as on-chip system efficiency, or the DRAM power should be included. This is important because Table 3 compares 'system efficiencies' across accelerators, and inconsistent power boundaries make the comparison misleading.
minor comments (5)
  1. [Section 4.2] The text says 'input data pre-infecting'; this should be 'pre-fetching'.
  2. [Section 4.3] The phrase 'tick channels' should likely be 'thin channels'; depthwise convolutions have few input channels, which explains the lower spatial utilization.
  3. [Figure 7 caption] The caption says 'normilized throughput'; it should be 'normalized throughput'.
  4. [Table 3] OpenGeMM's area is listed as 0.62 mm^2 in the table while Section 4.4 reports a cell area of 0.531 mm^2; the footnote explains this as layout area with 60% cell density, but the text should clarify which area value is used in the GOPS/mm^2 comparison.
  5. [Table 2] The definition of 'overall utilization' (OU) is not explicitly given; stating the formula (e.g., OU = SU × TU or cycle-based definition) would make the metric reproducible.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity: the headline utilization, speedup, and efficiency numbers are empirical RTL/power measurements, not derived from the claims they support.

full rationale

OpenGeMM's central claims are measured rather than derived. Utilization (81.89% to 99.34%) is a direct cycle count from Verilator RTL simulation of the generated accelerator, and the ablation isolates the three mechanisms against a baseline implementation. The 3.58x to 16.40x normalized throughput speedup versus Gemmini uses external performance data from reference [32], with the fairness caveat that process nodes, memory accounting, and configuration differ; that is a benchmarking concern, not a circular reduction. The 4.68 TOPS/W figure is computed as measured peak performance (204.8 GOPS) divided by measured power (43.8 mW), an empirical efficiency metric, not a prediction identical to an input. The only self-citations are design-space exploration and prior system references (e.g., ZigZag [20], NNASim [18], CMDS [17]), and these are used to motivate design choices that are also supported by independent reasoning in the text, such as the partial-sum precision argument for output-stationary dataflow. None of the measured results is fitted to the claim or defined in terms of the claim, so no step in the derivation chain is circular.

Assumptions & free parameters 4 free parameters · 5 assumptions · 0 invented entities

The paper is an empirical hardware design report. All parameters are explicit design-time knobs, not fitted constants. The main assumptions are methodological: excluding off-chip traffic, using an external Gemmini baseline, and relying on RTL synthesis rather than silicon.

free parameters (4)
  • GeMM array dimensions (Mu, Nu, Ku) = 8x8x8
    Hand-chosen case-study configuration in Table 1 to balance utilization and throughput; not fitted to the benchmark results.
  • Prefetch and output buffer depth = 2 for the main comparison; 3 and 4 explored
    Buffer depth is a design parameter varied in the ablation and directly changes utilization (Figure 5); the paper does not state which depth was used for the real DNN benchmarks in Table 2.
  • Integer precisions (PA, PB, PC) = 8, 8, 32
    Case-study precision; all reported TOPS/W and GOPS are for int8, so comparisons to other precisions are indirect.
  • Clock frequency and supply voltage = 200 MHz, 0.675 V
    Synthesis corner chosen for the case study; affects power and area numbers.
assumptions (5)
  • domain assumption Output-stationary dataflow is preferable to weight-stationary for GeMM because partial sums have higher precision than weights.
    Invoked in Section 2.3 to justify the temporal loop order; supported by design-space exploration citation [20], but remains a modeling choice.
  • domain assumption The multi-banked scratchpad with 16 read ports and 32 write ports provides sufficient bandwidth so that the measured utilization is limited by compute and streamer behavior, not by memory port contention.
    The case-study memory configuration in Table 1 underlies all utilization measurements; no sensitivity analysis across port counts is provided.
  • ad hoc to paper Off-chip DRAM-to-SRAM data movement cycles can be excluded when reporting performance and efficiency.
    Explicitly stated in footnote 2 of Section 4.3. This assumption is load-bearing for the speedup and utilization claims at system level.
  • domain assumption Gemmini's published performance data from [32] are a fair baseline for normalized throughput comparison.
    The paper does not run Gemmini in its own flow; it compares against numbers from a different paper with different technology and configuration.
  • domain assumption Synthesis and power analysis at 200MHz, 0.675V in 16nm, with 60% cell density layout estimation, predict real silicon behavior.
    All area, power, and TOPS/W numbers come from this design flow; no measured silicon is presented.

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Cite this review

Pith. "Pith review of OpenGeMM: A High-Utilization GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling." pith.science (2026). https://pith.science/paper/WH7LRBUT

@misc{pith2026241109543,
  author       = {Pith},
  title        = {Pith review of: OpenGeMM: A High-Utilization GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/WH7LRBUT}},
  note         = {Machine review of arXiv:2411.09543}
}
read the original abstract

Deep neural networks (DNNs) face significant challenges when deployed on resource-constrained extreme edge devices due to their computational and data-intensive nature. While standalone accelerators tailored for specific application scenarios suffer from inflexible control and limited programmability, generic hardware acceleration platforms coupled with RISC-V CPUs can enable high reusability and flexibility, yet typically at the expense of system level efficiency and low utilization. To fill this gap, we propose OpenGeMM, an open-source acceleration platform, jointly demonstrating high efficiency and utilization, as well as ease of configurability and programmability. OpenGeMM encompasses a parameterized Chisel-coded GeMM accelerator, a lightweight RISC-V processor, and a tightly coupled multi-banked scratchpad memory. The GeMM core utilization and system efficiency are boosted through three mechanisms: configuration pre-loading, input pre-fetching with output buffering, and programmable strided memory access. Experimental results show that OpenGeMM can consistently achieve hardware utilization ranging from 81.89% to 99.34% across diverse CNN and Transformer workloads. Compared to the SotA open-source Gemmini accelerator, OpenGeMM demonstrates a 3.58x to 16.40x speedup on normalized throughput across a wide variety ofGeMM workloads, while achieving 4.68 TOPS/W system efficiency.

Figures

Figures reproduced from arXiv: 2411.09543 by the authors.

Figure 1
Figure 1. OpenGeMM platform overview. 1 INTRODUCTION DNN models have been rapidly integrated into various aspects of our society, bringing a blossom of novel applications. However, they also bring a voracious demand for ever more computing power, pre￾senting significant challenges for efficient execution. This problem is particularly severe when deploying DNNs at the edge, such as in-vehicle and wearable devices, where string… view at source ↗
Figure 2
Figure 2. Dataflow representation in the GeMM accelerator [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. GeMM accelerator hardware generator microar [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (3 more)
Figure 4
Figure 4. Figure 4: (a) Scenario without configuration pre-loading, input pre-fetch, and output buffering. (b) Conceptual visualizations [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 6
Figure 6. Figure 6: OpenGeMM cell area and total power breakdown. 4.4 Area and Power Evaluation The workload for system power estimation involves block matrix multiplication with a size of (32, 32, 32). OpenGeMM system occu￾pies a cell area of 0.531 𝑚𝑚2 and consumes a total system power o…
Figure 7
Figure 7. Figure 7: Comparison of normilized throughput (GOPS/ [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]

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Forward citations

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