Hardware acceleration for ultra-fast Neural Network training on FPGA for MRF map reconstruction

Alessandra Retico; Alessandro Gabrielli; Camilla Marella; Claudia Testa; Fabrizio Alfonsi; Leonardo Brizi; Marco Barbieri; Mattia Ricchi

REVIEW 3 major objections 5 minor 13 references

Hardware acceleration for ultra-fast Neural Network training on FPGA for MRF map reconstruction

T0 review · 3 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read The paper claims that an FPGA can train the MRF reconstruction network in an estimated 200 seconds at a 200 MHz clock, roughly 200 times faster than the CPU training baseline, which would make on-device retraining practical whenever…

desk verdict A plausible feasibility pitch for on-device MRF retraining, undercut by a 200 s estimate built on incomplete cycle accounting and an internal contradiction about whether the full network fits. read the letter →

arxiv 2506.22156 v1 pith:WKTHYHXZ submitted 2025-06-27 cs.AR cs.CVphysics.ins-det

Mattia Ricchi , Fabrizio Alfonsi , Camilla Marella , Marco Barbieri , Alessandra Retico , Leonardo Brizi , Alessandro Gabrielli , Claudia Testa This is my paper · ORCID

classification cs.ARcs.CVphysics.ins-det

keywords magneticresonancefingerprintingneuralnetworktrainingFPGAaccelerationhardwareimplementationquantization-awarebackpropagationT1andT2mappingreal-timeMRI

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that neural-network training for Magnetic Resonance Fingerprinting (MRF) reconstruction can be moved onto an FPGA, and that on-hardware training would take under five minutes: about 200 seconds at a 200 MHz clock, compared with roughly 16 hours on CPU. If true, this changes the practical MRF workflow, because MRF is not standardized and any change in scanner, field strength, or reconstruction parameters currently forces an expensive retraining step. The authors adapt the existing nine-layer network by removing two layers and applying quantization-aware training, then implement the neuron and backpropagation operations in VHDL. They estimate that time-multiplexing a 16-node forward block and a 16-to-32-node backpropagation block covers the whole network, yielding the 200-second figure. The paper is best read as a feasibility argument backed by synthesis estimates and by identical outputs between the VHDL node and the Python implementation.

What carries the argument

The load-bearing device is time-multiplexed hardware reuse of two generic blocks: a 16-node forward block (each node takes 4 clock cycles, and all layers together take 56 cycles per sample) and a 16-to-32-node backpropagation block (3 cycles per node, 104 cycles total), run at a 200 MHz clock with a 5 ns period. These blocks are iterated over the whole quantized network, so the total training time is estimated as $5\,\mathrm{ns}\cdot 250{,}000{,}000\cdot(56+104)=200\,\mathrm{s}$. The supporting piece is the VHDL implementation of the single-neuron equation $y=\sigma(\sum_{i} x_i w_i + b)$ and the backpropagation delta equations, with identical outputs between hardware and Python for the same inputs, weights, and biases.

What would settle it

Run the actual training on an Alveo U250 with the same 250 million simulated MRF signals streamed over PCIe under the same 500-epoch, 1000-step schedule, and measure wall-clock time. If the measured time exceeds roughly five minutes by a significant margin, the 200-second estimate and the 200-times speedup over CPU do not hold.

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Extended reading notes

Core claim

The central claim is that both inference and training for the MRF neural network can be implemented on an FPGA, with training time dominated by a simple arithmetic budget: each training sample costs 56 clock cycles for forward propagation and 104 cycles for backpropagation, and with 250 million samples at a 5 ns clock period the total is 200 seconds. The paper grounds this in a concrete hardware picture: one generic node function in VHDL, 16 nodes deployed in a semiparallel block, a backpropagation module between layers of 16 and 32 nodes, repeated across the network, using 8 percent of the LUTs and 40 percent of the DSPs of an Alveo U250. It also shows that the quantized integer network keeps reconstruction quality close to the original, with MAPE for T1 rising from 2.15 to 2.36 percent and for T2 from 8.89 to 11.07 percent. The claim is not that a finished accelerator exists, but that the per-node arithmetic and resource budget already fit on the board, so the 200-second training estimate is presented as a realistic projection.

Load-bearing premise

The load-bearing premise is that reusing one 16-node forward block and one 16-to-32-node backpropagation block covers every layer of the whole network at a fixed cost of 56 plus 104 clock cycles per training sample, with no additional latency from memory access, data transfer, control logic, optimizer updates, or layer-to-layer differences.

Editorial extensions

If this is right

If the estimate holds, MRF reconstruction networks can be retrained on the scanner or on a nearby FPGA in minutes whenever acquisition parameters change, removing the main obstacle to MRF standardization.
The quantized network's error metrics stay close to the original, so the speed gain does not obviously come at the cost of reconstruction quality.
The resource figures (8 percent of LUTs and 40 percent of DSPs) suggest the same FPGA could host a second copy of the network for parallel processing, roughly doubling throughput.
FPGA-based training could lower energy per training run and make telemedicine scenarios practical, because the accelerator can sit inside the scanner rather than in a GPU cluster.
The same hardware approach extends to other MRF parameter sets: retraining for different T1/T2 ranges or field strengths is just another training run on the same blocks.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The 200-second figure counts only forward and backward arithmetic cycles; a wall-clock measurement would add PCIe transfer, memory access, control logic, and optimizer overhead, so the realized speedup is likely below 200 times until those costs are absorbed.
The FPGA port uses plain stochastic gradient descent while the software baseline used Adam; if convergence differs, the 500-epoch, 1000-step schedule may not be equivalent, which would shift the CPU-versus-FPGA comparison.
The estimate also ignores the cost of generating or loading the 250 million simulated training signals, which a fair comparison against the 16-hour CPU run would need to include.
A stronger end-to-end test would be to train the quantized network on the FPGA and compare the resulting T1/T2 maps against the reported quantized error metrics, separating speed gains from accuracy effects.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Colleague,

The one thing to know: this paper is not a demonstration of FPGA training. It is a feasibility study with one implemented neuron block and one backpropagation block, plus an extrapolated training-time figure. The extrapolation is the entire basis for the 200 s claim, and it does not hold together as stated.

What is genuinely new: prior FPGA work on MRF and medical NNs is inference-only. The motivation here, that MRF retraining is needed when acquisition parameters change and that mapping reconstruction and training onto an FPGA could remove that bottleneck, is a real and worthwhile problem. The authors also do some honest work: they implement a generic VHDL node and a backprop module, verify node outputs against Python, and report resource usage for the full design (145k LUTs, 5k DSPs, 146k FFs, 8% LUT and 40% DSP). If those resource numbers are accurate, fitting the whole quantized network is plausible, which is relevant.

Now the soft spots, in proportion. First, Eq. (3) is a lower bound, not a training time. The 56+104 cycles cover only forward and backward compute blocks as time-multiplexed; the Adam optimizer used on CPU is explicitly deferred, and data movement, PCIe transfer, memory access, control logic, and scheduling across layers are not counted. The stress-test note is right about this. Second, there is a direct contradiction: Section 3 first says the whole network and backpropagation cannot be implemented on the FPGA, then reports resource usage for the entire network and backpropagation and calls it 'entirely viable.' That needs to be resolved. Third, the speedup comparison to CPU is sloppy—the abstract says up to 250x, the text says 200x, and the CPU baseline is for the original, unquantized network, not the adapted one.

These flaws are load-bearing for the central quantitative claim, so I agree with the reader's reject verdict as a paper standing on its current evidence. But I would not dismiss the direction. The problem is well-motivated, the authors are transparent about what is implemented versus estimated, and the resource estimate is a useful data point. A serious revision that either implements the full training loop or clearly labels the 200 s as a back-of-envelope compute-cycle-only projection, plus fixes the contradiction, could be worth another look.

For peer review: I would send this to a referee. The application is real, the implementation pieces are checkable, and the flaws are correctable enough to justify referee time rather than a desk reject—though the expected outcome would be heavy revision.

Referee Report

3 major / 5 minor

Summary. The manuscript reports an FPGA-based implementation of a simplified, quantized fully connected network for MRF T1/T2 map reconstruction. The authors implement a generic node and a backpropagation module in VHDL, verify the node against Python, estimate resource usage on an Alveo U250 board, and extrapolate from Eq. (3) to claim a 200 s training time for 250M samples, about 200 times faster than CPU training. The paper's central quantitative claim is the 200 s estimate, and the reported contribution is the claim that on-device retraining of the MRF reconstruction network becomes practical.

Significance. If the 200 s estimate were supported by a complete, measured implementation, the result would be significant for MRF standardization and real-time deployment, since the network would need retraining whenever acquisition parameters change. The quantized network preserves accuracy reasonably well (T1 MAPE increases from 2.15% to 2.36%, T2 MAPE from 8.89% to 11.07%), and the hardware-software equivalence check for the single node is a useful verification step. The resource estimates (145k LUTs, 5k DSPs, 146k FFs) also suggest that the design is plausible in resource terms. However, the central training-time claim is an extrapolation from assumed cycle counts rather than a demonstrated or measured result, and the manuscript contains an internal contradiction about whether the full network and backpropagation can fit on the FPGA.

major comments (3)

[Section 2.2, Eq. (3)] The 200 s figure counts only 56 + 104 clock cycles per sample for forward and backward computation, but it does not include any cycles for data movement, PCIe transfer, weight/bias memory access, control logic, or optimizer updates. The CPU baseline uses Adam, while the implemented backpropagation is stochastic gradient descent, so the comparison is not an apples-to-apples accounting of a complete training step. The 56 and 104 cycle numbers are asserted without RTL simulation, timing analysis, or on-board measurement, so Eq. (3) should be read as a lower-bound assumption for compute cycles only, not a validated training-time estimate.
[Section 3, resource assessment] The text first states that 'the whole network and backpropagation algorithm cannot be implemented on the FPGA', then immediately reports 145k LUTs, 5k DSPs, and 146k FFs, which it says is 8% of LUTs and 40% of DSPs, and calls the implementation 'entirely viable from the resource point of view'. These statements are internally inconsistent. If the resource estimate covers the full network and backpropagation, then the time-multiplexing rationale for Eq. (3) is unnecessary; if it does not, then the 56 + 104 cycle count cannot represent the full training loop. This contradiction undermines the central claim.
[Section 2.2, time-multiplexing description] The manuscript does not specify how the 16-node forward block and the 16-to-32-node backpropagation block are iterated to cover all layers of the network, nor how many additional cycles are required for scheduling, weight updates, and control. The statement that 'by iterating these two blocks multiple times in a semiparallelised way, all the operational requirements of the network can be covered' is not accompanied by a layer-by-layer cycle breakdown, so the 56 and 104 cycle totals have no verifiable relation to the actual network architecture shown in Fig. 2.

minor comments (5)

[References] References [8] and [10] are the same work by Sanaullah et al.; one of them should be removed or renumbered.
[Abstract and Section 3] The abstract reports that CPU training 'can be up to 250 times slower', while Section 3 reports a speedup of '200 times'; since 16 hours versus 200 s corresponds to a factor of about 288, the speedup figures should be reconciled.
[Section 2.2] The board name is given as 'AL VEO U250'; the correct vendor name is 'Alveo U250'.
[Section 2.2, Eq. (3)] The notation '250′000′000' is nonstandard; it should be written as 250,000,000.
[Figures] The adapted network in Fig. 2 is not described in the text with explicit layer sizes, which makes it difficult to verify that the 16-node and 16-to-32-node blocks actually cover all layers.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation found; the 200-second training estimate is arithmetic from stated cycle counts, not a fit or a self-referential definition.

full rationale

The paper's central quantitative claim is Eq. (3): (5 ns) x 250,000,000 samples x (56 + 104) cycles = 200 s. This is a direct multiplication of an assumed clock period, an assumed number of training samples, and assumed per-sample cycle counts; it is not obtained by fitting a parameter to the quantity it claims to predict, nor by defining the training time in terms of itself. The cycle counts (56 forward, 104 backpropagation) are explicitly stated as consequences of the implemented 16-node block and the 16-to-32-node backpropagation module, so the arithmetic is self-contained. The paper does inherit its network, dataset, and baseline training time from the authors' prior work (Barbieri et al., [6][7]), but this is a legitimate starting point for an acceleration study rather than a load-bearing self-citation: the cited work supplies the architecture and data being accelerated, not the FPGA timing result. No uniqueness theorem is imported from the authors, no ansatz is smuggled in via citation, and no known result is renamed as a new prediction. The genuine weaknesses are evidentiary rather than circular: the 56+104-cycle budget excludes memory access, PCIe transfer, control logic, and optimizer updates, and Section 3 first says the whole network cannot be implemented on the FPGA and then reports resource usage that implies it fits (8% LUTs, 40% DSPs, 'entirely viable'). These are consistency and completeness concerns about whether Eq. (3) describes a realizable full training step, but they do not make the derivation circular. Accordingly, no circularity step is identified and the score is 0.

Assumptions & free parameters 6 free parameters · 5 assumptions · 0 invented entities

The central estimate rests on six hand-chosen or assumed quantities (latencies, cycle totals, clock frequency, dataset size) and five domain assumptions about the quantized network and time-multiplexing. No new physical entities are introduced. The viability of the 200 s claim depends almost entirely on these assumptions, especially the no-overhead time-multiplexing assumption.

free parameters (6)

per-node forward latency = 4 clock cycles
Hand-estimated from the VHDL node implementation; used to build the 56-cycle total for all forward levels.
backpropagation module latency = 3 clock cycles
Estimated for the backpropagation block; contributes to the 104-cycle total in Eq. (3).
cycles for all forward levels = 56
Chosen for semi-parallel execution across network layers; no breakdown is shown.
total backpropagation cycles = 104
Assumed iteration count over all layers during one training sample; used directly in Eq. (3).
clock frequency = 200 MHz
Declared feasible from synthesis of a single node and backpropagation module, not from the complete placed-and-routed design.
training set size = 250,000,000
Borrowed from the prior Barbieri dataset; Eq. (3) treats each sample as one forward/backward pass.

assumptions (5)

domain assumption Standard backpropagation equations (Eq. 2) apply unchanged to the quantized integer network.
The paper uses integer QAT weights but gives no analysis of gradient accuracy under integer arithmetic; the Adam optimizer is not implemented on FPGA.
domain assumption Synthesis results from a single node and a backpropagation module imply the full network can run at 200 MHz.
The 200 MHz clock frequency is extrapolated from small blocks, not from the full placed-and-routed design.
ad hoc to paper Iterating the 16-node and 16-to-32-node blocks covers all network operations with no extra clock cycles.
This is the core assumption behind the 56 and 104 cycle totals in Eq. (3); no control or data-routing overhead is included.
domain assumption The 250M simulated MRF signals from the authors' earlier work form a valid training set for the modified network.
The adapted network removes the first two layers, but training data and test protocol are inherited from Barbieri et al. without re-validation against clinical data.
domain assumption Quantization and layer removal preserve clinically acceptable reconstruction accuracy.
Table 1 shows similar error metrics, but it does not clearly identify which network is 'original' and which is 'quantized', and no clinical validation is reported.

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Cite this review

Pith. "Pith review of Hardware acceleration for ultra-fast Neural Network training on FPGA for MRF map reconstruction." pith.science (2026). https://pith.science/paper/WKTHYHXZ

@misc{pith2026250622156,
  author       = {Pith},
  title        = {Pith review of: Hardware acceleration for ultra-fast Neural Network training on FPGA for MRF map reconstruction},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/WKTHYHXZ}},
  note         = {Machine review of arXiv:2506.22156}
}

read the original abstract

Magnetic Resonance Fingerprinting (MRF) is a fast quantitative MR Imaging technique that provides multi-parametric maps with a single acquisition. Neural Networks (NNs) accelerate reconstruction but require significant resources for training. We propose an FPGA-based NN for real-time brain parameter reconstruction from MRF data. Training the NN takes an estimated 200 seconds, significantly faster than standard CPU-based training, which can be up to 250 times slower. This method could enable real-time brain analysis on mobile devices, revolutionizing clinical decision-making and telemedicine.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

13 extracted references · 9 canonical work pages

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Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.

[1] [1]

Magnetic Resonance Imag- ing 68, 1–4 (2020) https://doi.org/10.1016/j.mri.2019.12.006

Gore, J.C.: Artificial intelligence in medical imaging. Magnetic Resonance Imag- ing 68, 1–4 (2020) https://doi.org/10.1016/j.mri.2019.12.006

work page doi:10.1016/j.mri.2019.12.006 2020

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Annual Review of Biomedical Engineering 19(Volume 19, 2017), 221–248 (2017) https: //doi.org/10.1146/annurev-bioeng-071516-044442

Shen, D., Wu, G., Suk, H.-I.: Deep learning in medical image analysis. Annual Review of Biomedical Engineering 19(Volume 19, 2017), 221–248 (2017) https: //doi.org/10.1146/annurev-bioeng-071516-044442

doi:10.1146/annurev-bioeng-071516-044442 2017

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Nature 495, 187–92 (2013) https://doi.org/ 10.1038/nature11971

Ma, D., Gulani, V., Seiberlich, N., Liu, K., Sunshine, J., Duerk, J., Griswold, M.: Magnetic resonance fingerprinting. Nature 495, 187–92 (2013) https://doi.org/ 10.1038/nature11971

doi:10.1038/nature11971 2013

[4] [4]

Food Research International 161, 111779 (2022) https://doi.org/10.1016/ j.foodres.2022.111779

Christmann, J., Rohn, S., Weller, P.: Finding features - variable extraction strate- gies for dimensionality reduction and marker compounds identification in gc-ims data. Food Research International 161, 111779 (2022) https://doi.org/10.1016/ j.foodres.2022.111779

work page arXiv 2022

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Magnetic Resonance in Medicine 78 (2017) https://doi.org/10.1002/mrm.26580 7

Ma, D., Coppo, S., Chen, Y., Mcgivney, D., Jiang, Y., Pahwa, S., Gulani, V., Gris- wold, M.: Slice profile and b 1 corrections in 2d magnetic resonance fingerprinting: Mrf with slice profile and b 1 corrections. Magnetic Resonance in Medicine 78 (2017) https://doi.org/10.1002/mrm.26580 7

work page doi:10.1002/mrm.26580 2017

[6] [6]

Barbieri, M., Brizi, L., Giampieri, E., Solera, F., Castellani, G., Testa, C., Remon- dini, D.: Circumventing the Curse of Dimensionality in Magnetic Resonance Fingerprinting Through a Deep Learning Approach

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Physica Medica 89, 80–92 (2021) https://doi.org/10.1016/j.ejmp

Barbieri, M., Brizi, L., Giampieri, E., Solera, F., Manners, D., Castellani, G., Testa, C., Remondini, D.: A deep learning approach for magnetic resonance fingerprinting: Scaling capabilities and good training practices investigated by simulations. Physica Medica 89, 80–92 (2021) https://doi.org/10.1016/j.ejmp. 2021.07.013

doi:10.1016/j.ejmp 2021

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BMC bioinformatics 22(1), 421 (2021) https://doi.org/10.1186/ s12859-021-04347-6

Xiong, S., Wu, G., Fan, X., Feng, X., Huang, Z., Cao, W., Zhou, X., Ding, S., Yu, J., Wang, L., Shi, Z.: Mri-based brain tumor segmentation using fpga-accelerated neural network. BMC bioinformatics 22(1), 421 (2021) https://doi.org/10.1186/ s12859-021-04347-6

work page 2021