A Mixed-Signal Large Dynamic Range Front-End ASIC for High Capacitance Detectors

A.Rivetti; F.Cossio; M. Da Rocha Rolo; W.Cheng; Z.Wang

REVIEW 3 major objections 8 minor 11 references

A Mixed-Signal Large Dynamic Range Front-End ASIC for High Capacitance Detectors

T0 review · 3 major / 8 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read A 64-channel CMOS chip reports under 1% charge nonlinearity to 300 fC, 3500-electron noise at 100 pF, and 4 ns jitter at 14 fC for high-capacitance gaseous detectors.

desk verdict Real ASIC with solid 100 pF data; the 'hundreds of pF' headline is only supported by a simplified stability simulation. read the letter →

arxiv 1908.01163 v1 pith:XD52LLQR submitted 2019-08-03 physics.ins-det

W.Cheng , F.Cossio , M. Da Rocha Rolo , A.Rivetti , Z.Wang This is my paper · ORCID

classification physics.ins-det

keywords regulatedcommon-gatemixed-signalASIChighdynamicrangedetectorcapacitancegaseousdetectorstime-to-digitalconvertersample-and-holdtime-over-threshold

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper reports the design and electrical characterization of a 64-channel front-end chip for gaseous particle detectors whose capacitance can reach hundreds of picofarads. Each channel amplifies the detector current with a low-impedance regulated common-gate input, shapes it in fast and slow branches, and digitizes both the arrival time and the charge, so the chip delivers a fully digital event stream. The measurements show a programmable charge range up to 400 fC, an integral non-linearity below 1% up to 300 fC, an equivalent noise charge of about 3500 electrons at 100 pF input capacitance, and 4 ns timing jitter at 14 fC, at under 9 mW per channel. If these results carry over to real detectors, the chip is a plausible single-chip readout for GEM, MicroMEGAS, and MWPC detectors, saving external ADC and TDC circuitry.

What carries the argument

The load-bearing element is the regulated common-gate (RCG) current conveyor: a common-gate input transistor whose transconductance is boosted by a common-source amplifier of open-loop gain $A$. The input impedance becomes $Z_{in}=1/(A g_{m1})$, and the input pole is $\tau_i=C_d/(A g_{m1})$, so the pole is $A$ times higher than in a plain common-gate stage, which is what makes very large detector capacitance manageable. A stability analysis of the second-order transfer function shows that the circuit avoids complex-conjugate poles for very small and very large $C_d$, the regime where a transimpedance amplifier can become unstable, so the RCG is presented as the reason the chip can be specified for detectors with tens to hundreds of picofarads of capacitance.

What would settle it

Mount the chip on a real GEM, MicroMEGAS, or MWPC detector and compare the reconstructed charge and timing for known deposited charges with the injected-pulse results at the same input capacitance; if the real-detector integral nonlinearity exceeds 1% or the jitter at 14 fC with 100 pF exceeds 4 ns, the synthetic current-pulse-plus-capacitor test model is missing something.

Watch

Extended reading notes

Core claim

The paper's central claim is that a regulated common-gate (RCG) pre-amplifier lets a CMOS front-end keep a stable, fast, low-noise response while the detector capacitance is large, tens to hundreds of picofarads, and that the rest of the chain, fast and slow shapers, discriminators, TDCs, ADCs, and two charge-measurement modes, fits in 64 parallel channels at under 9 mW per channel. The fabricated 110 nm CMOS chip was characterized by injecting test pulses through an external capacitor, and the measurements show a programmable range up to 400 fC, an integral non-linearity below 1% up to 300 fC, an equivalent noise charge of about 3500 electrons at 100 pF, and 4 ns r.m.s. timing jitter at 14 fC with 100 pF. The paper also reports a roughly 20% excess noise over simulation, a not-fully-understood systematic jitter offset, and a minimum-gain nonlinearity that it attributes to PMOS output-stage modulation and proposes to fix with a cascoded output stage. The intended application is a single-chip digital readout for GEM, MicroMEGAS, and MWPC detectors.

Load-bearing premise

The chip was characterized with synthetic test pulses injected through an external capacitor rather than with real gaseous-detector signals, so the quoted performance is assumed to transfer to actual detector events with their real current waveforms and parasitics.

Editorial extensions

If this is right

Because each channel produces a fully digital payload with channel ID, time stamp, and charge, a detector readout built around this chip would not need separate external TDC and ADC boards.
The programmable gain and input impedance let one chip design serve GEM, MicroMEGAS, and MWPC detectors, whose capacitance and charge ranges differ.
The 40 ps TDC binning is small enough that the digitization contributes negligibly to the front-end's intrinsic time resolution at 50 fC.
The sample-and-hold path gives linear charge readout below 300 fC; the time-over-threshold path extends the usable range to 400 fC at the cost of a nonlinear calibration.
The RCG input's stability in the high-capacitance regime is what allows the 'hundreds of pF' operating point, which a conventional transimpedance amplifier could not reach without instability.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

A direct measurement at 200–500 pF input capacitance would test the 'hundreds of pF' claim, which is currently supported only by stability simulations up to 500 pF.
The same RCG input stage could in principle be reused for other high-capacitance sensors, such as large-area silicon strip detectors, since the input-pole and stability arguments do not depend on gaseous detectors specifically.
Combining sample-and-hold below 300 fC with calibrated time-over-threshold above it could give one channel both linearity and the full 400 fC range.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Read the ASIC paper. The bottom line is that this is a real engineering effort: a fabricated 64-channel front-end in 110 nm CMOS with a regulated common-gate preamp, two shapers, TDCs, ADCs, and S&H/ToT charge measurement modes. The electrical characterization is largely convincing: gain settings follow the expected pattern, INL is below 1% up to 300 fC, ENC at 100 pF is about 3500 e-, and the timing jitter is around 4 ns for 14 fC into 100 pF. The authors are also honest about the two clear defects—the 12% gain mismatch at the minimum gain setting and the INL degradation above 300 fC—and they propose a cascode fix. That is the right way to report a first prototype.

The soft spot is the abstract's 'high capacitance up to hundreds of pF' claim. Every measured point in the paper stops at 100 pF. The only support beyond that is a stability simulation of a simplified schematic (Table 3), and the transfer-function analysis shows exactly why that is not enough: the input pole and the stability boundaries depend directly on C_d. The measured noise also sits 20% above post-layout simulation, and the timing jitter shows a systematic offset that the authors do not fully explain. So a simulation-based extrapolation to 500 pF has no empirical anchor. The tests also used injected pulses with an external capacitor rather than a real gaseous detector, which is fine for an electrical characterization but does not establish detector compatibility.

This is not a fatal flaw. The chip works, the data are real, and the discrepancies are acknowledged. But the authors should either measure at a few hundred pF or soften the claimed input-capacitance range. If the 'hundreds of pF' statement stays in the abstract, it needs at least one measured point above 100 pF.

I would send this to peer review. It is a prototype ASIC paper with reproducible measurements and a clear architecture, and the limitations are mostly stated. The referee should ask for the high-capacitance measurement or a revised claim, and for a comment on the unexplained offsets. I would not cite the high-C claim in my own work; the noise analysis is standard, and the measured 100 pF numbers are useful but not a result I need.

Referee Report

3 major / 8 minor

Summary. The paper reports the design and electrical characterization of a 64-channel mixed-mode ASIC for the readout of gaseous detectors (GEM, MicroMEGAS, MWPC). Each channel contains a regulated common-gate (RCG) preamplifier with programmable gain, a fast timing shaper with discriminator, a slow energy shaper, a TDC based on analog interpolation, and charge measurement by Sample-and-Hold or Time-over-Threshold. The authors derive the RCG transfer function and stability conditions, describe the shaper and digitizer circuits, and present test results from a fabricated 110 nm CMOS chip. Measured results include programmable gain from roughly 1.2 to 9.7 mV/fC, S&H INL below 1% up to 300 fC, ENC of about 3500 e- at 100 pF input capacitance, timing jitter of about 4 ns at 14 fC with 100 pF, and power consumption near 9 mW per channel. The paper claims suitability for detector capacitances up to hundreds of pF, based on circuit analysis and stability simulations up to 500 pF, while the direct measurements are limited to 0-100 pF.

Significance. If the stated results hold, this is a useful prototype front-end for high-capacitance gaseous detectors, and the architecture combines features (RCG input, dual shapers, TDC, S&H/ToT) that are relevant to the BESIII CGEM and similar upgrades. The strengths of the paper are that the key performance numbers (gain, ENC, jitter, INL, power) come from direct measurements of a fabricated chip, not from fitting parameters, and that the measured data are compared with post-layout simulations. The paper is also transparent about known discrepancies, such as the 20% noise excess and the unexplained jitter offset. However, the headline capability for "hundreds of pF" detector capacitance is not supported by measured data, and the minimum-gain setting that enables the 400 fC dynamic range shows significant gain mismatch and INL. These gaps are load-bearing for the main claims and should be addressed before acceptance.

major comments (3)

[§6, Table 4] The abstract and Table 1 claim operation with detector capacitance "up to hundreds of pF", but the electrical characterization in §6 is limited to input capacitances of 0–100 pF: ENC in Fig. 15, jitter in Fig. 16, and the Table 5 summary are all quoted at 100 pF. The 350 pF and 500 pF entries in Table 3 come from a stability simulation of the simplified schematic of Fig. 4 using an ideal current source and parameters A0=50, τ_R=2 ns, Cgs1=1 pF, not from post-layout simulation or from measurements. Because the measured noise exceeds post-layout simulation by 20% and the jitter model of Eq. (6.1) shows a systematic unexplained offset, a simulation-only extrapolation from 100 pF to 500 pF lacks an empirical anchor. Please provide measurements at 200 pF, 350 pF, or 500 pF, or revise the claim to state that the verified range is 0–100 pF with stability simulation only beyond that range.
[§6, Eq. (6.1)] The minimum-gain setting (set8), which is the setting that reaches the headline 400 fC dynamic range, has 12.03% gain mismatch and 2.78% INL, and the text attributes this to PMOS devices in the output stage entering the linear region. Since set8 is the setting that provides the largest charge range, the measured "dynamic range up to 400 fC" claim is currently supported only with a caveat that a design fix is required. The paper should report the offline-calibrated INL over the full 400 fC range, or explicitly state the dynamic range as the region where the uncalibrated INL remains below 1%.
[§6] The jitter comparison in Fig. 16 shows a systematic offset of about 440 e- r.m.s. between measured and simulated timing jitter, and the authors state that the cause is not fully understood. Timing resolution is a central performance parameter (4 ns at 14 fC and 100 pF in Table 5), so the predictive model used to extrapolate to other operating points is not validated. Please provide a quantitative investigation of this offset (for example, discriminator threshold noise, digital interference, or time-walk effects) or report jitter with an explicit systematic-error band.

minor comments (8)

[§6] In the jitter discussion, the "440 e− r.m.s." offset is dimensionally an input-referred charge noise, while Fig. 16 shows time jitter in ns; please clarify the quantity and how it is converted from time to charge units.
[Table 4] Figure 15 contains duplicated χ²/ndf labels with two sets of fit parameters superimposed; please clean the figure so that only the correct fit results are shown.
[§5] In Table 4, the columns "Gain Test" and "Gain Simulated" lack explicit units and a definition of the mismatch percentage; please specify the measurement method (fast-shaper peak amplitude per injected charge) and the mismatch formula.
[Eqs. (3.15)-(3.16)] Reference [7] appears in the bibliography but is not cited in the text; the description of the four S&H buffers for event de-randomisation in §5 should cite it.
[Abstract and Table 5] The text says that complex-conjugate roots are avoided for very small or very large Cd, but complex-conjugate poles are not necessarily unstable; the phase-margin simulation in Table 3 is the more relevant stability metric, so the wording should be aligned.
[§6] The abstract states power consumption "less than 9 mW/channel", Table 5 reports "9 mW/ch", and Table 1 reports "<10 mW/ch"; please unify these values.
[§6] Figures 17 and 18 report data from "63ch" and "62ch" without explanation; please state whether one or more channels were excluded from the analysis and why.
[§6] The characterization uses injected test pulses rather than real gaseous-detector signals; please state explicitly how the C-R test-pulse injection represents the current-source-plus-capacitance detector model, since interconnection parasitics and the actual detector current waveform could affect the measured performance.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity found: performance claims are direct measurements compared with simulations; the high-capacitance extrapolation is a coverage gap, not a circular reduction.

full rationale

The paper's central claims are direct electrical characterizations: gain, ENC, timing jitter, INL, power, and dynamic range are measured on the fabricated chip and compared against post-layout simulations. No equation in the paper reduces to a parameter fitted on the same data it is said to predict. The jitter model, Eq. (6.1), computes simulated jitter from independently simulated output noise and slew rate, and the paper explicitly reports the measured offset as unexplained rather than re-fitting the model. The stability simulation at 350 pF and 500 pF (Table 3) uses a simplified schematic with stated parameters (A0=50, tau_R=2 ns, Cgs1=1 pF) and does not incorporate the measured results, so it is an extrapolation rather than a circular restatement. The self-citations to the TIGER ASIC and to earlier RCG work are design-heritage references and are not load-bearing in the derivation of the measured performance figures. The gap between the 'hundreds of pF' claim and the 100 pF maximum measured capacitance is a real evidentiary limitation, but it is a completeness/coverage concern, not a circularity concern. Overall, no circular reduction is present.

Assumptions & free parameters 1 free parameters · 4 assumptions · 0 invented entities

This is a hardware design paper, so the ledger consists of framing assumptions rather than mathematical postulates. The principal dependencies are the detector-as-current-source-capacitor model, the validity of small-signal approximations, the noise model, and trust in post-layout simulation; no new physical entities are introduced.

free parameters (1)

ToT calibration polynomial coefficients = not reported
Section 6: ToT charge reconstruction requires a 3rd-order polynomial fit or offline LUT; the reported ToT-vs-charge curves depend on this calibration, and the coefficients are not provided.

assumptions (4)

domain assumption Detector output can be modeled as a current pulse in parallel with a capacitor of tens to hundreds of pF.
Used in Section 1 and throughout characterization, where an external capacitor and test pulse emulate the detector.
domain assumption Small-signal approximations hold: Cd >> (A+1)Cgs1 and gm1(A+1) >> 1/ro1.
Section 3, Eqs. 3.5-3.6 justify the two-pole transfer function and input impedance used for design and stability.
domain assumption Thermal noise from NM1 and NM2 dominates, with A^2 gm1^2 >> gm2^2 making NM2 the dominant source.
Section 3, Eq. 3.19 is used to set transistor sizes and predict ENC.
domain assumption Post-layout simulation is representative of the fabricated silicon, apart from stated mismatches.
Simulation is the baseline for gain, noise, and jitter comparisons in Section 6; deviations are attributed to test environment and digital interference.

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Cite this review

Pith. "Pith review of A Mixed-Signal Large Dynamic Range Front-End ASIC for High Capacitance Detectors." pith.science (2026). https://pith.science/paper/XD52LLQR

@misc{pith2026190801163,
  author       = {Pith},
  title        = {Pith review of: A Mixed-Signal Large Dynamic Range Front-End ASIC for High Capacitance Detectors},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/XD52LLQR}},
  note         = {Machine review of arXiv:1908.01163}
}

read the original abstract

A 64-channel mixed-mode ASIC, suitable for particle detectors of large dynamic range and high capacitance up to hundreds of pF, is presented here. Each channel features an analogue front-end for signal amplification and filtering, and a mixed signal back-end to digitise and store the signal information. The analogue part consists of a low input-impedance programmable gain pre-amplifier based on a regulated common-gate (RCG) input stage, two shapers optimised for time and energy measurements. The back-end part mainly includes discriminators, TDCs and ADCs, which are used to process the signal and encode both the time of arrival and the charge in the input signal with a fully digital output. The programmable gain of the front-end (up to 400 fC input dynamic range) and the versatile back-end allow the readout of different gaseous detectors like GEM, MicroMEGAS and MWPC. The ASIC is designed for an event rate up to 100 kHz per channel and a power consumption less than 9 mW/channel, has been fabricated in a 110 nm CMOS technology.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

11 extracted references · 11 canonical work pages

[1]

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Sauli, Fabio. Gaseous radiation detectors: fundamentals and applications. Vol. 36. Cambridge University Press, 2014

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G. De Geronimo, Shaorui Li, "Shaper Design in CMOS for High Dynamic Range", IEEE Transactions on Nuclear Science, Vol. 58, no. 5, October 2011

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Pith tools

Reviewed August 14, 2026 · model on record in the stance chip above.

[1] [1]

Gaseous radiation detectors: fundamentals and applications

Sauli, Fabio. Gaseous radiation detectors: fundamentals and applications. Vol. 36. Cambridge University Press, 2014

work page 2014

[2] [2]

CMOS: front-end electronics for radiation sensors[M]

Rivetti A. CMOS: front-end electronics for radiation sensors[M]. CRC Press, 2015

work page 2015

[3] [3]

BESIII Cylindrical GEM Inner Tracker

BESIII Collaboration. BESIII Cylindrical GEM Inner Tracker. Technical report, July, 2014

work page 2014

[4] [4]

A cylindrical GEM detector with analog readout for the BESIII experiment

Amoroso, Antonio, et al. "A cylindrical GEM detector with analog readout for the BESIII experiment." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 824 (2016): 515-517

work page 2016

[5] [5]

A custom readout electronics for the BESIII CGEM detector

Rolo, M. Da Rocha, et al. "A custom readout electronics for the BESIII CGEM detector." Journal of Instrumentation 12.07 (2017): C07017

work page 2017

[6] [6]

A pixel front-end ASIC in 0.13 um CMOS for the NA62 experiment with on pixel 100 ps time-to-digital converter

Martoiu, S., et al. "A pixel front-end ASIC in 0.13 um CMOS for the NA62 experiment with on pixel 100 ps time-to-digital converter." 2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC). IEEE, 2009

work page 2009

[7] [7]

Analog peak detector and derandomizer for high-rate spectroscopy

De Geronimo, Gianluigi, Anand Kandasamy, and Paul O’Connor. "Analog peak detector and derandomizer for high-rate spectroscopy." IEEE Transactions on nuclear science 49.4 (2002): 1769-1773

work page 2002

[8] [8]

A low-noise CMOS front-end for TOF-PET

Rolo, M. D., et al. "A low-noise CMOS front-end for TOF-PET." Journal of Instrumentation 6.09 (2011): P09003. – 17 – Qin [fC] 5 10 15 20 25 30 35 40 Residuals/Range [%] 0.6− 0.4− 0.2− 0 0.2 0.4 0.6 Residual nonlinearity of 62ch (a) gain 12 mV/fC Qin [fC] 50 100 150 200 250 300 Residuals/Range [%] 0.6− 0.4− 0.2− 0 0.2 0.4 0.6 0.8 1 1.2 Residual nonlinear...

work page 2011