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OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis

T0 review · 5 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read OpenLS-DGF is an open-source flow that builds one adaptive logic-synthesis dataset spanning Boolean representation, logic optimization, and technology mapping; its OpenLS-D-v1 (966k circuits) supports four ML tasks.

desk verdict A genuinely useful multi-task dataset for EDA-ML, with the central equivalence claim for logic-blasting asserted rather than proven — worth reviewing, but verify before trusting. read the letter →

arxiv 2411.09422 v2 pith:XO6AHJOB submitted 2024-11-14 cs.AI

Liwei Ni , Rui Wang , Miao Liu , Xingyu Meng , Xiaoze Lin , Junfeng Liu , Guojie Luo , Zhufei Chu
show 5 more authors
Weikang Qian Xiaoyan Yang Biwei Xie Xingquan Li Huawei Li
This is my paper · ORCID
classification cs.AI
keywords logicsynthesismachinelearningdatasetgenerationBooleannetworksGraphMLtechnologymappingQoRpredictioncircuitranking
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

OpenLS-DGF aims to give the logic-synthesis machine-learning community a single, open, adaptive dataset-generation flow instead of the task-specific datasets used before. The paper describes a seven-step pipeline that starts from 46 combinational designs, applies 1,000 logic-optimization recipes per design, blasts each optimized And-Inverter Graph (AIG) into seven logic representations, maps each representation to ASIC and FPGA netlists, measures timing, and packages the result as over 966,000 Boolean circuits with quality-of-results metadata. The central claim is that one such dataset can support several distinct ML tasks at once—the paper demonstrates circuit classification, circuit ranking, QoR prediction, and probability prediction—so models for different synthesis stages can be trained and compared on identical circuits. If this is right, it would replace bespoke task-specific datasets with a standard resource and make ML work in logic synthesis measurable on a common ground.

What carries the argument

The carrying mechanism is the closed loop between the conversion pipeline and the paper's Circuit class. On the synthesis side, the logic-blasting step turns one optimized AIG per recipe into six further Boolean-network types; Theorem 1 asserts that the mapping step preserves node dependencies by matching nodes before and after blasting, and that each MAJ3 gate can stand in for an AND gate. On the data side, the Circuit class is a generic graph object that stores each node's type, name, fanins, and a 64-bit truth table, keeps the original Boolean-circuit index alongside an internal index, and converts GraphML into a graph-learning tensor format with identical node indices. That index-preserving bridge is what lets a single dataset item be loaded, simulated, relabeled, and repacked into task-specific sub-datasets without losing the connection to the original circuit.

What would settle it

Run an independent combinational equivalence check on a random sample, or the full set, of the generated OIG, XAG, MIG, PRIMARY, and GTG circuits against their source AIGs, and separately compare node-dependency graphs before and after the conversion; a single functionally inequivalent sampled circuit, or any mismatch in dependency structure, would falsify the framework's label-correctness claim.

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Extended reading notes

Core claim

OpenLS-DGF is presented as an adaptive, open-source flow that covers the three fundamental stages of logic synthesis—Boolean representation, logic optimization, and technology mapping—in seven steps. Starting from 46 combinational benchmark designs, it applies 1,000 random optimization recipes per design, then logic-blasts each optimized AIG into a family of seven Boolean-network types (AIG, OIG, XAG, MIG, PRIMARY, and GTG), maps each to ASIC and FPGA netlists, runs static timing analysis, and packages everything into per-design tensor files. The resulting OpenLS-D-v1 contains over 966,000 Boolean circuits, each stored in Verilog and GraphML with quality-of-results metadata; the paper claims its Theorem 1 guarantees the logic-blasting conversion preserves node dependencies and that all generated files are verified by combinational equivalence checking. Four downstream tasks—circuit classification, circuit ranking, QoR prediction, and probability prediction—are implemented on sub-datasets extracted from OpenLS-D-v1, with reported classification accuracy near 99.8%, ranking accuracy near 99.5%, area prediction errors between 0.69% and 1.17%, and probability prediction errors as low as 0.0008.

Load-bearing premise

The load-bearing premise is that every logic-blasting conversion, including the topological AIG-to-MIG conversion, preserves both Boolean equivalence and node dependencies for all 966,000 generated circuits.

Editorial extensions

If this is right

  • One OpenLS-D-v1 item can feed at least four tasks—classification, ranking, QoR prediction, and probability prediction—so ML models for different synthesis stages can be trained and compared on identical circuits from a single download.
  • Circuit ranking is introduced as a new task: if a model can rank Boolean representations before technology mapping, designers can skip the expensive mapping and timing runs for inferior variants.
  • QoR prediction on unseen recipes, unseen designs, and unseen recipe-design combinations is reported to reach mean absolute percentage errors between 0.69% and 1.17% for area and between 6.49% and 7.87% for timing, suggesting the dataset carries enough structure for generalization.
  • The observation that different Boolean representations of the same design can have non-overlapping QoR regions means representation choice is a real design decision, not a cosmetic one.
  • Because intermediate Verilog files and TCL scripts are preserved, researchers can insert additional synthesis steps at any point and regenerate only the affected dataset files.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial extension: the per-recipe indexing shared across all packaged files makes OpenLS-D-v1 ready-made for transfer-learning benchmarks—train a classifier or QoR predictor on one task and test whether the learned circuit embeddings transfer to ranking or probability prediction.
  • Editorial extension: the paper's observation that QoR intervals stabilize after a few hundred recipes suggests a cheap generation-time stopping rule—monitor the QoR distribution's spread and stop adding recipes once it stops changing, which would cut the reported 76-hour generation cost.
  • Editorial extension: because the Circuit class stores a 64-bit truth table per node, the dataset could support node-level functional-equivalence tasks, such as cut enumeration or resubstitution candidate generation, without any new conversion work.
  • Editorial extension: if the AIG-to-MIG conversion were ever formally verified as functional equivalence rather than topological matching, the dataset's guarantees would become stronger; a direct test would be to implement a supergate-based MIG mapper and compare its outputs with the topological conversion's outputs.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 5 minor

Summary. The paper introduces OpenLS-DGF, a seven-step dataset generation framework built on Yosys, ABC, LSILS, iEDA, and LogicFactory, which converts combinational designs into six Boolean network representations (AIG, OIG, XAG, MIG, PRIMARY, GTG) plus ASIC and FPGA netlists with area and timing QoR, packaged into PyTorch-ready files through a custom Circuit class. The released OpenLS-D-v1 dataset contains 46 designs and more than 966,000 Boolean circuits generated from 1,000 synthesis recipes per design. The authors demonstrate the dataset's versatility through four downstream tasks: circuit classification, circuit ranking, QoR prediction, and probability prediction, and argue that OpenLS-D-v1 supports adaptive sub-dataset extraction and incremental extension.

Significance. If the equivalence and packaging claims hold, OpenLS-D-v1 is a valuable community resource: it is larger and more multi-task oriented than OpenABC-D, stores both Verilog and GraphML representations, includes an open-source circuit engine, and is publicly released. The four tasks span the main stages of logic synthesis and the dataset provides a single artifact from which multiple task-specific sub-datasets can be derived. These strengths are substantial and make the work a credible contribution to ML-for-EDA. However, the validation is currently weaker than the central claims require: the equivalence proof for logic blasting is not a functional-equivalence proof, the verification chain in Step 7 is under-specified, and the downstream experiments are single-run demonstrations without error bars or adequate baselines. These are fixable concerns rather than reasons to reject the paper.

major comments (5)
  1. [Section III-B, Step 4 and Theorem 1] The proof of Theorem 1 asserts that logic blasting preserves dependency relationships because nodes can be precisely matched and each MAJ3 gate can implement AND. This is not a proof of Boolean functional equivalence: a node-wise structural mapping plus a functional-completeness argument does not imply that every multi-input subcircuit is replaced by a functionally equivalent one, especially for the 'topological node-wise conversion' used for MIG, for which no algorithm or invariant is described. Since circuit classification, ranking, QoR, and probability labels all assume that every one of the 966k circuits is Boolean-equivalent to its source design, this is a load-bearing gap. Please either provide a formal equivalence invariant for each conversion (including MIG), or report per-type combinational equivalence checking of every converted network against the original design, with pass rates.
  2. [Section III-B, Step 7] The verification statement says that LSILS-generated files are checked against their corresponding gate-level netlists in abc.aig.pt. This checks the mapped netlist against the possibly already-incorrect Boolean network from the same pipeline, not against the original source design; it therefore cannot certify that the stored circuits realize the intended functions. The paper also does not report how many files passed, which tool configurations were used, or whether any files failed and were discarded. Please specify the verification chain from the source design through each intermediate representation and give the pass/fail counts for all logic types.
  3. [Section V-E, Table VI] The QoR prediction setup is under-specified. The model outputs a softmax over 'the overall distribution', but the binning scheme (number of bins, boundaries, normalization, and how the QoR value is mapped to a bin index) is not defined, and the MAPE numbers in Table VI are reported without error bars, repeated trials, or comparison to a simple baseline such as predicting the median or mean of the training distribution. Without this information the reported area MAPE of 0.69% and timing MAPE of 6.49% cannot be reproduced or assessed. Please provide the binning details, the split sizes, and variance estimates.
  4. [Section V-F, Table VII] The probability prediction comparison is unclear: the 'Comparison' column in Table VII mixes PE improvements and time speedups with ambiguous notation, and the DeepGate2 and GraphSAGE baselines are not described in terms of architecture, features, training setup, or whether DeepGate2 is the published model or a reimplementation. No error bars or trial counts are given. As written, the table does not support the claim that the proposed method outperforms the baselines. Please specify the baselines and report means and standard deviations over multiple runs.
  5. [Sections V-C to V-F] Across all four downstream tasks, the experimental evidence is single-run and largely lacks baselines: classification is supported by a t-SNE plot and one accuracy number at epoch 10, ranking reports accuracy for one split without variance, and the QoR and probability tasks likewise report point estimates. While these experiments are presented as demonstrations of dataset applicability rather than as state-of-the-art benchmarks, the paper's claim that the dataset achieves 'prominent diversity and applicability' would be materially stronger if at least one task included a standard baseline, error bars, or multiple random seeds.
minor comments (5)
  1. [Section V-D, Problem Formulation] The text writes 'OoR' where 'QoR' is intended; please fix the typo.
  2. [Section V-D, Fig. 14] The caption of Fig. 14 says 'all three models achieve high accuracy', but the figure and surrounding text present a single model; Table V lists three models but no per-model figure is shown.
  3. [Fig. 2] The label 'PRIMAYR' should read 'PRIMARY'.
  4. [Section IV-A-2] The cosine similarity matrix is normalized to [0.3, 0.6], which makes the reported average similarity of 0.44 an artifact of the normalization rather than a raw similarity value; please report raw values or justify the normalization.
  5. [Table IV] The per-design counts in the table sum to 21,000 only if the 7,000 ASIC and 7,000 FPGA netlists are counted as part of the total; the grouping would be clearer if Boolean network counts and netlist counts were listed separately.

Circularity Check

1 steps flagged · score 2.0 of 10

One local proof-by-construction in Theorem 1; the four downstream tasks and dataset labels rest on external tools, so the circularity is minor and non-systemic.

  1. self definitional [Section III-B, Step 4 (Logic Blasting), Theorem 1 and its proof]
    "Theorem 1. The logic blasting method preserves the dependency relationships of the original circuit. Proof 1. The logic blasting step relies on the mapping step, ensuring that nodes between the circuits, both before and after the blasting, can be precisely matched. Thus, they retain the same topological structure. The matched nodes preserve the dependency relationships. Additionally, each MAJ3 gate can represent an AND gate, and it is still feasible to meet Theorem 1."

    The theorem's conclusion (preservation of dependency relationships) is asserted to follow from the mapping step that, by construction, matches nodes and preserves topological structure; if 'preserving dependency relationships' means exactly that matched nodes retain the same topology, the theorem restates its premise rather than proving an independent fact. It does not establish Boolean functional equivalence, and the MAJ3 sentence only notes that MAJ3 can implement AND, which does not show that the node-wise MIG conversion preserves the function at each node. Since Lemma 1 and the claim that all seven logic types are valid representations of the same design rely on this theorem, a circular proof leaves the dataset's central validity assertion underived.

full rationale

The dataset generation chain is otherwise non-circular. Labels and QoRs are produced by external tools (Yosys, ABC, LSILS, iEDA) from established benchmarks, and the four downstream tasks are standard supervised evaluations whose inputs are circuits and whose targets are measured or simulated quantities; no fitted parameter is renamed as a prediction, and no self-citation is load-bearing. The Theorem 1 proof is best read as a definitional statement about structural node matching rather than an independent derivation of equivalence; the paper's actual functional-equivalence check (Step 7) and the use of mature external synthesis tools provide independent support, so the circularity is local and minor. The Graph2Vec-based diversity analysis is self-referential because embeddings are computed on the generated data, but it is an internal quality metric rather than a derivation, and it does not raise the score beyond a small adjustment.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

No new physical, mathematical, or postulated entities are introduced. OpenLS-D-v1 is a dataset artifact rather than an invented entity. The framework uses existing gate libraries, EDA tools, and standard GNN components.

free parameters (3)
  • recipe_count = 1000
    Hand-set number of random optimization sequences per design; determines dataset scale and the claimed QoR distribution coverage without a convergence test.
  • recipe_length = 10
    Each recipe is a random sequence of 10 commands from a 14-command pool; no sensitivity analysis is given.
  • truth_table_bits = 64
    Truth tables standardized to 64 bits in the circuit engine; an implementation choice with no stated justification for all gates.
assumptions (4)
  • standard math The gate sets in Table II (AIG, OIG, XAG, MIG, PRIMARY, GTG) are functionally complete.
    Used in Definition 1 and throughout Step 4 to justify that any Boolean function can be represented in each logic type.
  • domain assumption Yosys, ABC, LSILS, and iEDA correctly perform their claimed synthesis, mapping, and timing analyses.
    Steps 1, 2, 3, 5, and 6 rely on these external tools for correctness of the generated circuits and QoR labels.
  • domain assumption The combinational equivalence checks mentioned in Step 7 are complete and correctly applied to all 966k circuits.
    The paper states 'All generated raw files undergo verification using combinational equivalence-checking tools' but gives no details on tool parameters or pass rate.
  • domain assumption Random simulation with sufficiently many input vectors yields accurate node probabilities.
    Task 4 labels each node with a probability computed by random simulation; the number of vectors is not specified.

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Cite this review

Pith. "Pith review of OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis." pith.science (2026). https://pith.science/paper/XO6AHJOB

@misc{pith2026241109422,
  author       = {Pith},
  title        = {Pith review of: OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/XO6AHJOB}},
  note         = {Machine review of arXiv:2411.09422}
}
read the original abstract

This paper introduces OpenLS-DGF, an adaptive logic synthesis dataset generation framework, to enhance machine learning~(ML) applications within the logic synthesis process. Previous dataset generation flows were tailored for specific tasks or lacked integrated machine learning capabilities. While OpenLS-DGF supports various machine learning tasks by encapsulating the three fundamental steps of logic synthesis: Boolean representation, logic optimization, and technology mapping. It preserves the original information in both Verilog and machine-learning-friendly GraphML formats. The verilog files offer semi-customizable capabilities, enabling researchers to insert additional steps and incrementally refine the generated dataset. Furthermore, OpenLS-DGF includes an adaptive circuit engine that facilitates the final dataset management and downstream tasks. The generated OpenLS-D-v1 dataset comprises 46 combinational designs from established benchmarks, totaling over 966,000 Boolean circuits. OpenLS-D-v1 supports integrating new data features, making it more versatile for new challenges. This paper demonstrates the versatility of OpenLS-D-v1 through four distinct downstream tasks: circuit classification, circuit ranking, quality of results (QoR) prediction, and probability prediction. Each task is chosen to represent essential steps of logic synthesis, and the experimental results show the generated dataset from OpenLS-DGF achieves prominent diversity and applicability. The source code and datasets are available at https://github.com/Logic-Factory/ACE/blob/master/OpenLS-DGF/readme.md.

Figures

Figures reproduced from arXiv: 2411.09422 by the authors.

Figure 1
Figure 1. The Logic Synthesis flow. TABLE I: The logic gates pool in this framework. Logic Gate Boolean Expression f(A, B, C) Distinctive shape Primitive Gates1 ... ... MAJ3 A · B + A · C + B · C M A B C f NAND3 A · B · C A B C f NOR3 A + B + C A B C f MUX21 C · B + C · A C A B f NMUX21 C · A + C · B C B A f AOI21 A · B + C f A B C OAI21 (A + B) · C f A B C • We implemented four typical downstream tasks utilizing the OpenLS-D… view at source ↗
Figure 2
Figure 2. The adaptive logic synthesis dataset generation framework of OpenLS-DGF. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Components of an item in OpenLS-D-v1. For conve [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figures from the paper (10 more)
Figure 5
Figure 5. Figure 5: Node correspondence between the three types of graph: [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: The graph embedding similarity of the source designs. [PITH_FULL_IMAGE:figures/full_fig_p008_6.png]
Figure 7
Figure 7. Figure 7: The QoR distribution for source designs. Each row illustrates the QoR distribution across different designs, and each [PITH_FULL_IMAGE:figures/full_fig_p009_7.png]
Figure 8
Figure 8. Figure 8: The distribution of node size and graph depth for one design with incremental recipe size of AIG sets. [PITH_FULL_IMAGE:figures/full_fig_p009_8.png]
Figure 11
Figure 11. Figure 11: The GNN-based Model for the circuit classification [PITH_FULL_IMAGE:figures/full_fig_p010_11.png]
Figure 10
Figure 10. Figure 10: Adaptive sub-dataset extraction framework of [PITH_FULL_IMAGE:figures/full_fig_p010_10.png]
Figure 13
Figure 13. Figure 13: illustrates the architecture of the pair-wise graph ranking model. We first combine these two Boolean circuits C0 and C1 into a block matrix. Then a GNN-based graph embedding will learn the combined embedding of these two circuits. Finally, the MLP-based compassion ne…
Figure 14
Figure 14. Figure 14: Pair-wise prediction distribution of the evaluation. [PITH_FULL_IMAGE:figures/full_fig_p011_14.png]
Figure 16
Figure 16. Figure 16: QoR predictions vs. ground truth of variant 1. (a)-(d) [PITH_FULL_IMAGE:figures/full_fig_p012_16.png]
Figure 17
Figure 17. Figure 17: The node embedding model. TABLE VII: Average prediction error and time comparison by the different node embedding methods, while the comparison column represents DeepGate2/GraphSAGE. recipes Model GraphSAGE DeepGate2 Comparison PE Time(s) PE Time(s) PE Time(x) 100 0.0…

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Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.