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Mobile Machine Learning Hardware at ARM: A Systems-on-Chip (SoC) Perspective

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arxiv 1801.06274 v2 pith:XRM7RSE7 submitted 2018-01-19 cs.LG cs.ARcs.NE

classification cs.LGcs.ARcs.NE
keywords hardwarelearningmachinemobilearchitectsefficiencyoptimizationaccelerator
verification ladder T0 review T1 audit T2 compute T3 formal

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Machine learning is playing an increasingly significant role in emerging mobile application domains such as AR/VR, ADAS, etc. Accordingly, hardware architects have designed customized hardware for machine learning algorithms, especially neural networks, to improve compute efficiency. However, machine learning is typically just one processing stage in complex end-to-end applications, involving multiple components in a mobile Systems-on-a-chip (SoC). Focusing only on ML accelerators loses bigger optimization opportunity at the system (SoC) level. This paper argues that hardware architects should expand the optimization scope to the entire SoC. We demonstrate one particular case-study in the domain of continuous computer vision where camera sensor, image signal processor (ISP), memory, and NN accelerator are synergistically co-designed to achieve optimal system-level efficiency.

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Cited by 1 Pith paper

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  1. A Computational Model for Tensor Core Units

    cs.DS 2019-08 conditional novelty 6.0 of 10

    The paper introduces the (m,ℓ)-TCU computational model for tensor-core accelerators and derives asymptotic running-time bounds for a portfolio of algorithms under it.

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