Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
CVC Verilog Compiler -- Fast Complex Language Compilers Can be Simple
As of 9 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 1 inbound Pith citation observation for arXiv:1603.08059.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-09T06:31:02.800959+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-01T22:23:39.449032Z
A source-named dated measurement, never combined with another source.
Source: cited_works
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation b7856683-bc4a-4cee-9c8c-d1a15060ec52 · inbound
Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis cites this paper.
Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis CVC Verilog Compiler -- Fast Complex Language Compilers Can be Simple
Reference 20
- Resolution
- unresolved
- no resolver link, observed 2026-08-01T22:23:39.449032Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.