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CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design

T0 review · 4 major / 5 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read One self-supervised, multimodal circuit encoder beats task-specific supervised models on five design-quality prediction tasks, and retrieving similar known circuits enables zero-shot prediction.

desk verdict CircuitFusion is a genuinely new multimodal RTL encoder with a plausible design, but the headline PPA numbers rest on only 8 test circuits with no significance testing, so the quantitative claims are provisional. read the letter →

arxiv 2505.02168 v1 pith:YNSWXNTF submitted 2025-05-04 cs.AR

Wenji Fang , Shang Liu , Jing Wang , Zhiyao Xie This is my paper · ORCID
classification cs.AR
keywords circuitrepresentationlearningmultimodalRTLdesignqualitypredictionself-supervisedpre-trainingretrieval-augmentedinferencePPAestimationfunctionallyequivalenttransformationchipautomation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

CircuitFusion seeks to establish that one general-purpose circuit encoder can do the work of many task-specific models in chip design. It represents every circuit at the granularity of a single register's logic cone, in three modalities at once: the hardware code itself, a structural graph of logic operators, and an LLM-written plain-language summary of what the logic does. The fused encoder is pre-trained with self-supervised tasks that exploit facts unique to circuits — logic can be rewritten into functionally identical but structurally different forms, and an RTL description and its synthesized netlist are the same circuit at two design stages. On five early-stage design quality prediction tasks, the paper reports that this one approach consistently beats the state-of-the-art task-specific supervised model for each task, with 5 to 13 percentage points lower mean absolute percentage error after fine-tuning, and even enables zero-shot prediction by retrieving the quality metrics of the most similar known circuits. If the claim holds, designers could get timing, power, and area feedback on freshly written code without running synthesis and without commissioning a new model per task.

What carries the argument

The load-bearing unit is the register-boundary sub-circuit, called a sub-circuit in the paper: backtracing all combinational logic that feeds one register yields a slice describing exactly one state transition in one clock cycle, and applying the same split to the synthesized netlist keeps the RTL and netlist views functionally aligned by construction. Each sub-circuit is expressed in three modalities — HDL code, an operator graph, and an LLM-generated functionality summary — and encoded by three unimodal encoders: a graph transformer, a BERT-initialized summary transformer, and a frozen LLM text encoder for long code. A summary-centric fusion encoder then cross-attends the summary tokens against a mixup of graph and code embeddings. Four self-supervised objectives train this stack: masked graph modeling; intra- and cross-modal InfoNCE contrastive learning with functionally equivalent transformations as positive samples; masked summary modeling plus summary–mixup matching; and a cross-stage contrastive alignment between RTL fusion embeddings and a pre-trained netlist graph encoder. The same unit carries inference: embeddings of known sub-circuits are stored in a vector store, the measured quality metrics of the most similar retrieved sub-circuits are concatenated with the target embedding, and a lightweight regressor maps the combined vector to the prediction — this retrieval mechanism is what delivers both the fine-tuning gains and zero-shot prediction.

What would settle it

Recompute the five-task comparison on a larger held-out set — say 30 or more complete designs, from benchmark families or design styles not used in pre-training — and check whether the reported 5 to 13 percentage point MAPE advantage over the task-specific baselines persists. In the same test, replace the retrieved reference metrics with metrics from randomly chosen dissimilar circuits: if prediction error is unchanged, retrieval is not doing the work the paper attributes to it.

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Extended reading notes

Core claim

The paper's claim is that circuits are inherently multimodal and that prior circuit representation learning, which reads only the structural graph, leaves most of the information needed for design-quality prediction unused. The discovery is that fusing three aligned views — Verilog code, an operator-level graph, and a generated functionality summary — at the grain of a register-boundary sub-circuit, and aligning the resulting representation with the gate-level netlist during pre-training, produces a representation that transfers across tasks. Pre-training combines four objectives: masked graph modeling and intra-modal contrastive learning whose positive pairs come from functionally equivalent transformations; cross-modal contrastive alignment; masked summary modeling with summary–mixup matching in a summary-centric cross-attention fusion encoder; and a contrastive alignment that pulls RTL fusion embeddings toward netlist graph embeddings. At inference, embeddings of known sub-circuits are indexed, and the measured quality metrics of the most similar retrieved sub-circuits are concatenated with the target embedding before regression, which improves fine-tuning and alone constitutes zero-shot prediction. Evaluated on five tasks, the single CircuitFusion model beats the task-specific state of the art on every task (12% vs 17% MAPE on slack, 11% vs 16% on WNS, 15% vs 25% on TNS, 13% vs 26% on power, and 11% vs 16% on area), and it beats general text and software code encoders by larger margins.

Load-bearing premise

The load-bearing premise is that eight held-out test circuits (the 20% side of an 80/20 split of 41 designs) can reliably gauge prediction quality: four of the five headline metrics are one number per entire design, and no variance or significance testing is reported.

Editorial extensions

If this is right

  • One pre-trained encoder covers many tasks: the same frozen CircuitFusion, fine-tuned with a lightweight regressor in about five minutes per task, beats the specialized supervised model built for each of the five tasks, removing the need for task-specific feature engineering.
  • Zero-shot prediction is possible: for designs with no fine-tuning labels, retrieving the top-1 most similar known sub-circuits and using their measured quality metrics as the prediction yields 21% MAPE on slack, versus 50–57% for general text and code encoders doing the same retrieval.
  • The application-side strategies transfer: adding sub-circuit splitting (S1) and retrieval-augmented inference (S4) to generic encoders such as the LLM text encoder and software code encoders improves their MAPE noticeably, though CircuitFusion still leads.
  • Performance scales with model and data: increasing the pre-trained model from 270M to 500M parameters lowers average fine-tuned error from about 19% to 12%, and growing pre-training data from 25% to 100% of the corpus gives a comparable drop.
  • Faster design iteration: because the predictions happen at the RTL stage, designers receive timing, power, and area feedback before running synthesis, and the paper notes the same predictions can feed early timing-optimization settings in synthesis flows.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • My inference: the register-cone split is a reusable currency beyond quality prediction — since each sub-circuit encodes one complete state transition, the same embedding index could support functional search over IP blocks, verification triage, or retrieval-conditioned RTL generation, all testable with the released model and no further pre-training.
  • My inference: retrieval-augmented inference assumes the vector store covers the distribution of new designs, which the paper does not test; error should grow as retrieved circuits become functionally less similar, and that degradation could be measured by ablating the store across benchmark families.
  • My inference: the implementation-aware alignment principle extends to later design stages — aligning circuit embeddings to floorplan, clock-tree, or layout data, not just netlists, should further sharpen early-stage predictions, and the same contrastive recipe could be reused directly.
  • My inference: because contrastive positives are generated by Boolean-equivalent transformations, the embedding space is organized by functional equivalence rather than surface syntax; a testable consequence is that structurally different implementations of the same function should embed as near neighbors, which would make the encoder useful for design-space exploration.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes CircuitFusion, a multimodal and implementation-aware circuit encoder for RTL-stage design quality prediction. Circuits are split into register-bound sub-circuits, each represented by HDL code, a structural graph, and a GPT-generated functionality summary. Three unimodal encoders feed a cross-attention fusion encoder, which is pre-trained with four self-supervised tasks, including masked graph modeling, intra- and cross-modal contrastive learning, masked summary modeling, and alignment with a netlist encoder. For downstream tasks, the authors propose retrieval-augmented inference, which retrieves similar known sub-circuits and uses their quality metrics as references, supporting both fine-tuning and zero-shot prediction. Across five tasks (slack, WNS, TNS, power, area), the paper reports consistent MAPE improvements of 5 to 13 percentage points over task-specific SOTA baselines, together with ablations of the proposed strategies and modalities.

Significance. If the reported results are statistically reliable, CircuitFusion is a useful step toward general RTL-stage circuit representations: it is the first such encoder to fuse three circuit modalities and to explicitly align RTL with post-synthesis netlists, and the retrieval-augmented inference idea is practical and clearly explained. The paper ships an open-source repository and includes detailed ablations of strategies and modalities, which strengthens reproducibility. However, the headline claim of consistent state-of-the-art performance is currently supported by only 8 test designs for four of the five tasks, with no significance testing; retrieval hyperparameter k is selected on the test set; and the closest prior encoder from the same group is cited but not compared against. These issues leave the central quantitative claim plausible but not yet statistically secured.

major comments (4)
  1. [Section 4, Table 2] The circuit-level evaluations for WNS, TNS, power, and area rest on only 8 test designs (33/8 split by complete design), with each metric being a single number per design. The paper reports no per-design breakdown, no variance across splits or seeds, and no significance test. With n=8, the reported 5-13 percentage-point MAPE improvements could be driven by a few favorable designs. Please report per-design errors, add multiple splits or bootstrap confidence intervals, and state whether the improvements are statistically significant.
  2. [Section 4.4, Table 3] The retrieval hyperparameter k is selected on the test set: the text states 'we set the retrieval number to 1' based on Table 3, which reports test-set top-k results. Selecting hyperparameters on the test set can inflate both the fine-tuned and zero-shot numbers. Please select k on a validation split, or report results across a range of k without test-set-based selection, and discuss the sensitivity of the final numbers to this choice.
  3. [Section 4.4, Figure 4] The zero-shot retrieval setting is a label lookup from a vectorstore containing known circuits' quality metrics, and the store is built from the same four open-source benchmark families as the 8 test designs. Top-1 retrieval may therefore return near-duplicate sub-circuits carrying near-identical labels, which makes the zero-shot results hard to interpret as generalization to unseen implementations. Please quantify retrieval similarity (e.g., distance of retrieved neighbors), and report a version in which same-design or same-benchmark-family sub-circuits are excluded from the store.
  4. [Related Works and Section 4.2] The authors cite their own prior ASP-DAC 2025 encoder (Fang et al., 2025), described as a self-supervised, pre-trained, cross-stage-aligned circuit encoder, but this direct predecessor is not included as a baseline in Table 2 or the ablations. Since CircuitFusion appears to extend that framework with multimodal fusion, sub-circuit splitting, and retrieval, at least one comparison against it is needed to isolate the incremental contributions claimed in the paper.
minor comments (5)
  1. [Table 2 vs Table 10] The WNS MAPE for NV-Embed-v1 is reported as 17% in Table 2 but 26% in the 'ori' row of Table 10. Please clarify which value corresponds to the same evaluation setup.
  2. [Section 3.3, Eq. (8)] Equation (8) defines an InfoNCE-style loss but labels it NCE, while the text frequently refers to CL; please define CL consistently as the InfoNCE loss used throughout the paper.
  3. [Figures 9 and 10] The ablation bar charts show single numbers without error bars or markers of variance; adding error bars across seeds or at least stating the number of runs would make the ablation claims more robust.
  4. [Introduction and Related Works] The claim of being the 'first multimodal and implementation-aware circuit encoder' should be qualified with respect to earlier multimodal timing predictors such as Wang et al. (2023b), which also fuse multiple circuit representations; the novelty claim would be stronger if framed as first to fuse HDL code, graph, and summary for a general RTL-stage encoder.
  5. [Appendix G, Table 12] The multi-clock experiment appears to use only two combined designs; please state explicitly that this is an illustrative case study rather than a full evaluation of multi-clock support.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: predictions are trained on external EDA-generated PPA labels and evaluated on held-out designs; retrieval labels and self-citations are inputs, not constructions of the target results.

full rationale

The derivation chain is an empirical pretrain-finetune pipeline, not a symbolic derivation. The pre-training objectives (Eqs. 1-7) use masked graph/summary modeling, contrastive alignment, and RTL-netlist alignment; none of these losses uses the downstream PPA labels as a target. The fine-tuning labels (slack, WNS, TNS, power, area) are produced by Synopsys Design Compiler and PrimeTime on a NanGate 45nm library, which is external ground truth generated independently of the model. The comparisons against RTL-Timer, MasterRTL, SNS v2, and text/code encoders are against published methods, not against re-derivations of CircuitFusion's own outputs. The summary modality is generated from the HDL code by GPT-4, so it carries no independent PPA information; the retrieval vectorstore contains known-circuit labels, so zero-shot inference is essentially k-NN label lookup, but both are explicit inputs to the method rather than assumptions that make the target equal to the input by construction. The main weaknesses are statistical: only 8 complete designs are held out for circuit-level WNS/TNS/power/area, and Section 4.4 chooses the retrieval number k from test-set results ('we set the retrieval number to 1 in our retrieval-augmented inference to minimize error'), which can inflate the reported margins. These are evaluation-protocol concerns, not circularity, because no reported number is forced by a fitted parameter or by the pre-training objective. Self-citations to the authors' prior encoders are used as baselines and related work, not as the sole justification for the central claim. The paper is self-contained against external benchmarks, so the circularity score is low.

Assumptions & free parameters 5 free parameters · 6 assumptions · 0 invented entities

The central claim is empirical; it rests on pretraining data, hyperparameters, and the assumption that benchmark circuits resemble real designs. No novel physical or mathematical entities are introduced.

free parameters (5)
  • InfoNCE temperature tau = 0.3
    Set for all contrastive losses; affects embedding alignment and downstream retrieval quality.
  • Loss weights for cross-modal and implementation-aware alignment = 0.2 vs intra-modal 1.0
    Chosen by hand to balance pretraining tasks; no search or sensitivity analysis is reported.
  • Graph masking ratio = 30%
    Chosen for masked graph modeling; affects structural pretraining quality.
  • Retrieval count k = 1
    Selected from Table 3 zero-shot results on the evaluation set, a post-hoc choice that can inflate reported performance.
  • Mixup interpolation coefficient lambda = not specified
    Controls graph-code pre-fusion; the value is not reported, so exact replication depends on the released code.
assumptions (6)
  • domain assumption GPT-4-generated functionality summaries faithfully describe each subcircuit's function and implementation details.
    Summaries are used both as a pretraining modality and as the query in fusion; if summaries are inaccurate, semantic alignment is trained on flawed annotations. See Section 3.1 and Figure 2b.
  • domain assumption Register-boundary splitting yields functionally equivalent, complete state-transition cones in both RTL and netlist.
    Sub-circuit splitting (S1) underpins all three modalities and cross-stage alignment; if cones do not align, the contrastive alignment is meaningless. See Section 3.1 and Algorithm 1.
  • domain assumption Equivalent transformations via Yosys/ABC produce positive samples with the same functionality but different structure.
    Used as positive pairs in contrastive learning; if transformations change function, embeddings are pulled together for the wrong reason. See Section 4 dataset description.
  • domain assumption Cosine similarity in the learned embedding space tracks functional similarity for retrieval.
    Retrieval-augmented inference (S4) depends on nearest-neighbor search returning functionally similar circuits; no direct evaluation of retrieval quality is provided. See Section 3.5.
  • domain assumption A small set of 8 test designs is representative of general RTL-stage prediction difficulty.
    Circuit-level PPA metrics are one number per design; with n=8, confidence intervals are wide and conclusions are fragile. See Section 4.
  • domain assumption The open-source benchmark designs and 45nm synthesis flow produce labels representative of industrial practice.
    Labels come from Synopsys Design Compiler with NanGate 45nm; transferability to industrial PDKs and complex clocking is untested. See Appendix B.1.

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Cite this review

Pith. "Pith review of CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design." pith.science (2026). https://pith.science/paper/YNSWXNTF

@misc{pith2026250502168,
  author       = {Pith},
  title        = {Pith review of: CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/YNSWXNTF}},
  note         = {Machine review of arXiv:2505.02168}
}
read the original abstract

The rapid advancements of AI rely on the support of ICs. However, the growing complexity of digital ICs makes the traditional IC design process costly and time-consuming. In recent years, AI-assisted IC design methods have demonstrated great potential, but most methods are task-specific or focus solely on the circuit structure in graph format, overlooking other circuit modalities with rich functional information. In this paper, we introduce CircuitFusion, the first multimodal and implementation-aware circuit encoder. It encodes circuits into general representations that support different downstream circuit design tasks. To learn from circuits, we propose to fuse three circuit modalities: hardware code, structural graph, and functionality summary. More importantly, we identify four unique properties of circuits: parallel execution, functional equivalent transformation, multiple design stages, and circuit reusability. Based on these properties, we propose new strategies for both the development and application of CircuitFusion: 1) During circuit preprocessing, utilizing the parallel nature of circuits, we split each circuit into multiple sub-circuits based on sequential-element boundaries, each sub-circuit in three modalities. 2) During CircuitFusion pre-training, we introduce three self-supervised tasks that utilize equivalent transformations both within and across modalities. 3) When applying CircuitFusion to downstream tasks, we propose a new retrieval-augmented inference method, which retrieves similar known circuits as a reference for predictions. It improves fine-tuning performance and even enables zero-shot inference. Evaluated on five different circuit design tasks, CircuitFusion consistently outperforms the SOTA supervised method specifically developed for every single task, demonstrating its generalizability and ability to learn circuits' inherent properties.

Figures

Figures reproduced from arXiv: 2505.02168 by the authors.

Figure 1
Figure 1. Preview of results on the effectiveness of proposed strategies and circuit modalities. [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Multimodal and multi-stage circuit preprocessing flow. We split circuits into sub-circuits [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. CircuitFusion pre-training workflow. CircuitFusion includes three unimodal encoders [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (7 more)
Figure 4
Figure 4. Figure 4: CircuitFusion retrieval-augmented inference flow. For downstream tasks, CircuitFusion [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]
Figure 5
Figure 5. Figure 5: Visualization of cross attention between summary and code/graph. [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]
Figure 6
Figure 6. Figure 6: On the downstream task perfor￾mance scaling with pre-trained CircuitFusion model size and data size. In [PITH_FULL_IMAGE:figures/full_fig_p010_6.png]
Figure 7
Figure 7. Figure 7: An example for multimodal circuit B.2.1 HDL CODE As shown in Figure 7a, the HDL code for each sub-circuit is directly used as one of the input modalities, capturing the functional description of the circuit’s behavior at the RTL stage. In this Verilog HDL code, a modul…
Figure 8
Figure 8. Figure 8: Retrival-augmented inference implementation for tasks at different granularities. [PITH_FULL_IMAGE:figures/full_fig_p018_8.png]
Figure 9
Figure 9. Figure 9: Ablation study on the effectiveness of proposed strategies. [PITH_FULL_IMAGE:figures/full_fig_p021_9.png]
Figure 10
Figure 10. Figure 10: Ablation study on the impact of circuit modalities. [PITH_FULL_IMAGE:figures/full_fig_p022_10.png]

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Forward citations

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  4. VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code

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Pith tools

Reviewed August 16, 2026 · model on record in the stance chip above.