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TrapSIMD: SIMD-Aware Compiler Optimization for 2D Trapped-Ion Quantum Machines

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arxiv 2504.17886 v2 pith:YT34ZZAG submitted 2025-04-24 quant-ph

classification quant-ph
keywords simdfluxtraptransportarchitecturalcompilerconstraintsexecutionhardware
verification ladder T0 review T1 audit T2 compute T3 formal
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abstract

Modular trapped-ion (TI) architectures offer a scalable quantum computing (QC) platform, with native transport behaviors that closely resemble the Single Instruction Multiple Data (SIMD) paradigm. We present FluxTrap, a SIMD-aware compiler framework that establishes a hardware-software co-design interface for TI systems. FluxTrap introduces a novel abstraction that unifies SIMD-style instructions -- including segmented intra-trap shift SIMD (S3) and global junction transfer SIMD (JT-SIMD) operations -- with a SIMD-enriched architectural graph, capturing key features such as transport synchronization, gate-zone locality, and topological constraints. It applies two passes -- SIMD aggregation and scheduling -- to coordinate grouped ion transport and gate execution within architectural constraints. On NISQ benchmarks, FluxTrap reduces execution time by up to $3.82 \times$ and improves fidelity by several orders of magnitude. It also scales to fault-tolerant workloads under diverse hardware configurations, providing feedback for future TI hardware design.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Efficient LLM-Generated Shuttling Compilers for Complex Trapped-Ion Architectures

    quant-ph 2026-07 conditional novelty 7.0 of 10

    Unmodified frontier LLMs generate correct, competitive trapped-ion shuttling compilers from specs, cutting timesteps up to 76% versus hand-crafted baselines and exposing large connectivity effects.

  2. Scaling Qubit Mapping and Routing With Position Graph Abstraction and Memoization

    quant-ph 2026-05 unverdicted novelty 6.0 of 10

    Position graph abstraction with memoized SABRE heuristics scales qubit mapping and routing for TI-QCCD architectures by caching repeated evaluations without altering decisions.

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