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The waves-in-space Purcell effect for superconducting qubits
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abstract
Quantum information processing, especially with quantum error correction, requires both long-lived qubits and fast, quantum non-demolition readout. In superconducting circuits this leads to the requirement to both strongly couple qubits, such as transmons, to readout modes while also protecting them from associated Purcell decay through the readout port. So-called Purcell filters can provide this protection, at the cost of significant increases in circuit components and complexity. However, as we demonstrate in this work, visualizing the qubit fields in space reveals locations where the qubit fields are strong and cavity fields weak; simply placing ports at these locations provides intrinsic Purcell protection. For a $\lambda/2$ readout mode in the `chip-in-tube' geometry, we show both millisecond level Purcell protection and, conversely, greatly enhanced Purcell decay (qubit lifetime of 1~$\mu$s) simply by relocating the readout port. This method of integrating the Purcell protection into the qubit-cavity geometry can be generalized to other 3D implementations, such as post-cavities, as well as planar geometries. For qubit frequencies below the readout mode this effect is quite distinct from the multi-mode Purcell effect, which we demonstrate in a 3D-post geometry where we show both Purcell protection of the qubit while spoiling the quality factor of higher cavity harmonics to protect against dephasing due to stray photons in these modes.
Forward citations
Cited by 2 Pith papers
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Intrinsic Multi-Mode Interference for Passive Suppression of Purcell Decay in Superconducting Circuits
Breaking the symmetry of a transmon capacitor activates multi-mode interference that can suppress Purcell decay, shown analytically, in simulation, and in one four-qubit device.
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Exceeding the Parametric Drive Strength Threshold in Nonlinear Circuits
Strong low-frequency parametric drive on a transmon causes ionization above a threshold that matches Floquet predictions, limiting parametric gate speed.
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