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arxiv: 1907.00527 · v1 · pith:YWESQNFNnew · submitted 2019-07-01 · 💻 cs.IT · math.IT

Polar Codes with Memory

Wenyue Zhou , Qiang Liu , Yifei Shen , Xiaofeng Zhou , Chuan Zhang , Yaohua Xu , Liping Li This is my paper

Pith reviewed 2026-05-25 11:54 UTC · model grok-4.3

classification 💻 cs.IT math.IT
keywords polar codespolar codes with memorypacket error ratesuccessive cancellation decodingbelief propagation decodingsuccessive cancellation list decodinghardware decodermutual information bits
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The pith

Polar codes with memory pair consecutive blocks to reduce packet error rate to the square of the base rate at unchanged complexity.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces polar codes with memory by linking two consecutive code blocks with a controlled share of mutual information bits. A successful decode of one block then supplies those bits to help recover the other. This design makes the overall packet error rate scale as the square of the error rate of the underlying polar code. It applies to any standard decoder without raising complexity. The result is performance gains shown in both analysis and hardware implementations.

Core claim

PCM consists of pairs of consecutive polar code blocks that share a controlled number of mutual information bits. The shared bits from a succeeded block assist the decoder of the failed block. Analysis establishes that this reduces the packet error rate to the order of the square of the PER of the stand-alone polar code while preserving the original decoding complexity. The same holds when the underlying decoder is SC, BP or SCL. Simulations confirm PCM-SC performs within 0.3 dB of stand-alone SCL with list size two, and PCM-SCL with list size L matches stand-alone SCL with list size 2L.

What carries the argument

The PCM pairing of consecutive blocks that shares a controlled number of mutual information bits so that success in one aids the other's recovery.

If this is right

  • Packet error rate falls from order PER to order PER squared.
  • PCM-SC achieves performance comparable to stand-alone SCL with list size two.
  • PCM-SCL with L lists matches stand-alone SCL with 2L lists.
  • The low-latency interleaved hardware decoder reduces worst-case latency to 16.1 percent of adaptive SCL while raising throughput by a factor of 13 for block length 256.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The memory pairing could be extended to chains longer than two blocks to produce higher-order error-rate scaling.
  • The number of shared bits could be made adaptive according to observed channel conditions or prior block outcomes.
  • The same cross-block sharing principle might improve error-rate scaling in other code families that already support list or belief-propagation decoders.

Load-bearing premise

The shared mutual information bits from a succeeded block can be used by the decoder to meaningfully assist recovery of the failed block.

What would settle it

A measurement or analysis that shows the PCM packet error rate does not scale as approximately the square of the stand-alone polar code PER when the shared bits are supplied to the decoder.

Figures

Figures reproduced from arXiv: 1907.00527 by Chuan Zhang, Liping Li, Qiang Liu, Wenyue Zhou, Xiaofeng Zhou, Yaohua Xu, Yifei Shen.

Figure 2
Figure 2. Figure 2: The input bit arrangement of PCM. Even. These mutual information bits are placed at the same indices, and the mutual information set is denoted as B. The input bit stream arrangement is shown in [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: The input bit arrangement of the general [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figure 6
Figure 6. Figure 6: The simulated PER of the PCM-SC-2 and the analyzed PER in Eq. (9). The parameters are the same as those in [PITH_FULL_IMAGE:figures/full_fig_p008_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: PER of the PCM-SCL-2 over AWGN chan￾nels. The parameters are the same as those in [PITH_FULL_IMAGE:figures/full_fig_p008_7.png] view at source ↗
Figure 10
Figure 10. Figure 10: IS PCM-SC-2 decoder. 2-interleaved SC polar decoder [11], and it can reduce decoding latency remarkably with only a small increase in hardware consumption compared with the IS architecture. A. In-serial PCM-SC-2 Decoder In order to increase hardware utilization and reduce computational complexity, the decoder pro￾cesses the data in the form of log-likelihood ratio (LLR) instead of LR. The top-level archit… view at source ↗
Figure 9
Figure 9. Figure 9: PER of the PCM-SC-3 over AWGN chan￾nels. The parameters are the same as those in [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
Figure 11
Figure 11. Figure 11: LLI PCM-SC-2 decoder. ƌĞĂŬƉŽŝŶƚ ŵĞŵŽƌLJ Žϭ D ŽϮ Žϯ /ϭ /Ϯ Žϭ ŽϮ Žϯ /ϭ /Ϯ     D D D D Žϭ D ŽϮ Žϯ /ϭ /Ϯ Žϭ ŽϮ Žϯ /ϭ /Ϯ     D D D D [PITH_FULL_IMAGE:figures/full_fig_p010_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Processing element of LLI architecture. decoded block are effectively fed to the bit memory of incorrectly decoded block. B. Low-latency Interleaved PCM-SC-2 Decoder It should be noticed that when it comes to Case 2 and Case 3, the decoding latency of the IS PCM￾SC-2 decoder is 1.5 times of the conventional SC decoder. When Block Odd or Block Even performs a new round of decoding, the computation of LLRs … view at source ↗
Figure 13
Figure 13. Figure 13: Reduction rate of the average latency for [PITH_FULL_IMAGE:figures/full_fig_p011_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Average latency of the IS PCM-SC-2 de￾coder and the LLI PCM-SC-2 decoder (in clock cycles). round decoding by 49.3% and 66.9% at Eb/N0 = 1 dB and Eb/N0 = 4 dB, respectively [PITH_FULL_IMAGE:figures/full_fig_p011_14.png] view at source ↗
read the original abstract

Polar codes with memory (PCM) are proposed in this paper: a pair of consecutive code blocks containing a controlled number of mutual information bits. The shared mutual information bits of the succeeded block can help the failed block to recover. The underlying polar codes can employ any decoding scheme such as the successive cancellation (SC) decoding (PCM-SC), the belief propagation (BP) decoding (PCM-BP), and the successive cancellation list (SCL) decoding (PCM-SCL). The analysis shows that the packet error rate (PER) of PCM decreases to the order of PER squared while maintaining the same complexity as the underlying polar codes. Simulation results indicate that for PCM-SC, the PER is comparable to (less than 0.3 dB) the stand-alone SCL decoding with two lists for the block length $N=256$. The PER of PCM-SCL with $L$ lists can match that of the stand-alone SCL decoding with $2L$ lists. Two hardware decoders for PCM are also implemented: the in-serial (IS) decoder and the low-latency interleaved (LLI) decoder. For $N=256$, synthesis results show that in the worst case, the latency of the PCM LLI decoder is only $16.1\%$ of the adaptive SCL decoder with $L=2$, while the throughput is improved by 13 times compared to it.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper proposes Polar Codes with Memory (PCM), a construction that pairs consecutive polar code blocks sharing a controlled number of mutual information bits so that a succeeded block can assist recovery of a failed block. The underlying polar codes may use SC, BP, or SCL decoding. The central claim is that this yields packet error rate (PER) scaling as O(PER²) at the same complexity as the base polar code; simulations for N=256 show PCM-SC within 0.3 dB of stand-alone SCL with two lists, PCM-SCL matching SCL with twice the list size, and two hardware decoder architectures (IS and LLI) with reported latency and throughput gains.

Significance. If the O(PER²) scaling is established by a rigorous bound on the conditional error probability after assistance, the construction would provide a complexity-preserving route to quadratic PER improvement for polar codes, which is of practical interest for short-blocklength regimes. The hardware results, if reproducible, would further indicate concrete latency/throughput benefits over adaptive SCL.

major comments (2)
  1. [Abstract / analysis] Abstract and analysis section: the claim that PER_PCM scales as O(PER²) requires that, conditional on one block succeeding and sharing its mutual-information bits, the assisted block's error probability drops to O(PER). The text states only that the shared bits 'can help' recovery and that blocks are otherwise independent; no equation or bound is visible quantifying that the controlled number of shared bits suffices to move the effective channel into the high-reliability regime for the dominant error events. Without this step the quadratic scaling does not follow.
  2. [Simulation results] Simulation results for N=256: the reported PER curves and the statement that PCM-SC is 'comparable to (less than 0.3 dB)' stand-alone SCL with L=2 lack visible error bars, data-exclusion rules, or the precise SNR range over which the comparison holds. This makes it impossible to assess whether the observed gap is statistically consistent with the claimed O(PER²) improvement.
minor comments (2)
  1. [Hardware implementation] The hardware decoder descriptions (IS and LLI) would benefit from an explicit latency formula or timing diagram that isolates the contribution of the memory-sharing path.
  2. [PCM construction] Notation for the shared mutual-information bits (size, location within the polar graph) is introduced only descriptively; a short equation or figure label would clarify the construction.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments. We address the two major comments below and will revise the manuscript accordingly to strengthen the presentation.

read point-by-point responses

  1. Referee: [Abstract / analysis] Abstract and analysis section: the claim that PER_PCM scales as O(PER²) requires that, conditional on one block succeeding and sharing its mutual information bits, the assisted block's error probability drops to O(PER). The text states only that the shared bits 'can help' recovery and that blocks are otherwise independent; no equation or bound is visible quantifying that the controlled number of shared bits suffices to move the effective channel into the high-reliability regime for the dominant error events. Without this step the quadratic scaling does not follow.

    Authors: The analysis in the manuscript relies on block independence and the fact that a successful block provides reliable mutual-information bits that assist the failed block, leading to the claimed O(PER²) scaling. We agree that an explicit bound on the conditional error probability is not derived in the current text. In the revision we will add a short derivation in the analysis section that bounds the assisted-block error probability by O(PER) when the shared bits are taken from a correctly decoded block, thereby rigorously justifying the quadratic scaling. revision: yes

  2. Referee: [Simulation results] Simulation results for N=256: the reported PER curves and the statement that PCM-SC is 'comparable to (less than 0.3 dB)' stand-alone SCL with L=2 lack visible error bars, data-exclusion rules, or the precise SNR range over which the comparison holds. This makes it impossible to assess whether the observed gap is statistically consistent with the claimed O(PER²) improvement.

    Authors: The curves were obtained via Monte-Carlo simulation; however, the manuscript does not report confidence intervals or the exact trial counts. We will revise the simulation section and figures to include binomial confidence intervals (error bars), state the minimum number of blocks simulated per SNR point, and specify the SNR interval over which the 0.3 dB comparison is made. revision: yes

Circularity Check

0 steps flagged

No significant circularity in derivation chain

full rationale

The PCM construction pairs blocks and shares a controlled number of mutual-information bits so that success of one assists the other. The O(PER^2) scaling is stated to follow from this pairing plus standard polar-code analysis; no equation is shown to define the assisted conditional error rate in terms of the target PER itself, no parameter is fitted on a subset and then relabeled a prediction, and no uniqueness theorem or ansatz is imported via self-citation. The central claim therefore remains an independent consequence of the block-pairing mechanism rather than a tautology.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 1 invented entities

The central claim rests on the new PCM block-pairing construction and standard polar code polarization properties; no explicit free parameters are fitted in the abstract, and the shared-bit mechanism is the primary invented element without external falsifiable evidence provided.

axioms (1)
  • standard math Standard channel polarization and mutual information properties of polar codes under SC, BP, and SCL decoding.
    The paper extends polar codes, which rely on these established information-theoretic results.
invented entities (1)
  • Polar codes with memory (PCM) construction no independent evidence
    purpose: Pairing consecutive blocks with shared mutual information bits for cross-block recovery assistance
    New scheme introduced to achieve the PER-squared scaling; no independent evidence outside the paper is cited in the abstract.

pith-pipeline@v0.9.0 · 5788 in / 1292 out tokens · 74619 ms · 2026-05-25T11:54:30.201746+00:00 · methodology

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Reference graph

Works this paper leans on

12 extracted references · 12 canonical work pages

  1. [1]

    Channel polarization: A method for constructing capacity-achieving codes for symmetric binary-input memo ry- less channels,

    E. Ar ıkan, “Channel polarization: A method for constructing capacity-achieving codes for symmetric binary-input memo ry- less channels,” IEEE Trans. Inf. Theory , vol. 55, no. 7, pp. 3051–3073, 2009

    work page 2009

  2. [2]

    Performance of po lar codes for channel and source coding,

    N. Hussami, S. Korada, and R. Urbanke, “Performance of po lar codes for channel and source coding,” in Proc. IEEE Int. Symp. Inf. Theory , June 2009, pp. 1488–1492

    work page 2009

  3. [3]

    List decoding of polar codes,

    I. Tal and A. V ardy, “List decoding of polar codes,” IEEE Trans. Inf. Theory , vol. 61, no. 5, pp. 2213–2226, 2015

    work page 2015

  4. [4]

    CRC-aided decoding of polar codes,

    K. Niu and K. Chen, “CRC-aided decoding of polar codes,” IEEE Commun. Lett. , vol. 16, no. 10, pp. 1668–1671, October 2012

    work page 2012

  5. [5]

    Improved successive cancell ation decoding of polar codes,

    K. Chen, K. Niu, and J. Lin, “Improved successive cancell ation decoding of polar codes,” IEEE Trans. Commun., vol. 61, no. 8, pp. 3100–3107, August 2013

    work page 2013

  6. [6]

    A performance comparison of polar codes and reed- muller codes,

    E. Ar ıkan, “A performance comparison of polar codes and reed- muller codes,” IEEE Commun. Lett., vol. 12, no. 6, pp. 447–449, 2008

    work page 2008

  7. [7]

    On bit error rate performan ce of polar codes in finite regime,

    A. Eslami and H. Pishro-Nik, “On bit error rate performan ce of polar codes in finite regime,” in Proc. Annual Allerton Conf. on Commun., Control, Computing (Allerton) , 2010, pp. 188–194

    work page 2010

  8. [8]

    An FPGA implementation of succes- sive cancellation list decoding for polar codes,

    A. S¨ ural and E. Ar ıkan, “An FPGA implementation of succes- sive cancellation list decoding for polar codes,” Ph.D. dis serta- tion, Bilkent Univ., Ankara, 2016

    work page 2016

  9. [9]

    How to construct polar codes,

    I. Tal and A. V ardy, “How to construct polar codes,” IEEE Trans. Inf. Theory , vol. 59, no. 10, pp. 6562–6582, October 2013

    work page 2013

  10. [10]

    Low-latency sequential and over lapped architectures for successive cancellation polar decoder,

    C. Zhang and K. Parhi, “Low-latency sequential and over lapped architectures for successive cancellation polar decoder, ” IEEE Trans. Signal Process. , vol. 61, no. 10, pp. 2429–2441, May 2013

    work page 2013

  11. [11]

    Interleaved successive cance llation polar decoders,

    C. Zhang and K. K. Parhi, “Interleaved successive cance llation polar decoders,” in Proc. 2014 IEEE Int. Symp. Circuits Syst. (ISCAS), June 2014, pp. 401–404

    work page 2014

  12. [12]

    High throughput decoding methods and archi tecture for polar codes with high energy-efficiency and low latency,

    O. Dizdar, “High throughput decoding methods and archi tecture for polar codes with high energy-efficiency and low latency, ” Ph.D. dissertation, Bilkent Univ., Ankara, 2017

    work page 2017