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REVIEW 3 major objections 5 minor 13 references

RH: An Architecture for Redesigning Quantum Circuits on Quantum Hardware Devices

T0 review · 3 major / 5 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read The paper claims that prepending identical random quantum circuits to an entangling quantum generative adversarial network turns a state-learning method into a unitary-learning architecture, letting quantum hardware verify and reconstruct…

desk verdict Useful heuristic for circuit equivalence checking on hardware, but the completeness theorem is not proven as stated and the 'large-scale complete' claim needs to be walked back. read the letter →

arxiv 2412.20893 v3 pith:YXORZBAB submitted 2024-12-30 quant-ph

Runhong He , Ji Guan , Xin Hong , Guolong Cui , Shengbin Wang , Shenggang Ying This is my paper · ORCID
classification quant-ph MSC 81P6868Q12 PACS 03.67.Lx
keywords quantumcircuitredesignequivalencecheckingentanglinggenerativeadversarialnetworkunitarylearningrandomcircuitsvariationalreconstructiondestructiveSWAPtestnoisyintermediate-scale
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper sets out a way to redesign quantum circuits directly on quantum hardware, without classically simulating the full unitary. The idea is to prepend two identical random quantum circuits to an entangling quantum generative adversarial network, so the network no longer learns just a single output state but the whole unitary transformation implemented by a reference circuit. The paper argues this gives a complete verification procedure: if the trained discriminator says two circuits match for random input states, then their difference matrix $D = U^{\dagger}U'$ must be the identity. It also introduces a shallow local random circuit that makes the required random inputs practical, and demonstrates the architecture on equivalence checking of parameterized and non-parameterized circuits and on variational circuit reconstruction, both in simulation and on a superconducting processor.

What carries the argument

The machinery has four parts. The load-bearing identity is $D = U^{\dagger}U'$, the difference matrix, together with the fidelity condition $|\langle\varphi|D|\varphi\rangle|^2 = 1$; Theorem 1 says a unitary satisfying this for arbitrary random states is the identity. The probe states are prepared by two copies of a random circuit placed before the reference and generator circuits, and the paper's practical proposal is a local random circuit made of single-qubit rotations that produces product states with mutually independent amplitudes. The comparator is the parameterized destructive SWAP test, whose failure probability $p_{\mathrm{failure}} = 1 - |\langle\phi|\psi\rangle|^2$ is trained to be robust against coherent CZ errors. The paper also explicitly analyzes a worst-case difference matrix $D = I_2^{\oplus(n-1)} \oplus U_s$, where an error acting on an exponentially small subspace is missed with probability about $e^{-m/2^{n-1}}$ for $m$ measurements.

What would settle it

Run the RH test on a pair of circuits whose difference matrix is the paper's worst-case form, $D = I_2^{\oplus(n-1)} \oplus U_s$ with a nontrivial $U_s$ acting on an exponentially small subspace, and measure the false-negative rate as a function of shot count $m$ and qubit number $n$; if the observed miss probability does not approach $e^{-m/2^{n-1}}$, or if at large $n$ the error is routinely missed with feasible shot counts, the architecture's practical completeness claim fails.

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Extended reading notes

Core claim

The central claim is that the RH architecture, built from two identical random state-preparation circuits followed by a reference circuit, a generator circuit, and a trained parameterized destructive SWAP-test discriminator, learns and verifies arbitrary unitary transformations rather than merely quantum states. The paper defines the difference matrix $D = U^{\dagger}U'$ between the reference and generator unitaries and proves that if $D$ fixes every random input state, then $D$ is the identity, so the two circuits are equivalent. This completeness argument turns a collection of state-overlap tests into a proof of circuit identity, and the paper supplements it with the observation that the trained discriminator can compensate for coherent two-qubit gate errors. The architecture is then demonstrated on three tasks: checking equivalence of non-parameterized and parameterized circuits, and variationally reconstructing a target circuit from a structurally different ansatz, with benchmarks reported on a superconducting processor and on circuits of four to nine qubits in classical simulation.

Load-bearing premise

The completeness guarantee rests on the assumption that the random input states used in the test are rich enough that a unitary fixing every one of them must be the identity; with finitely many states and finitely many shots, a non-equivalent pair can slip through undetected.

Editorial extensions

If this is right

  • Equivalence checking of quantum circuits can be moved onto the quantum device: instead of classically simulating a large circuit, one runs the two circuits side by side with identical random inputs and reads off the test-failure probability.
  • Parameterized circuit equivalence becomes checkable by sampling random parameter values, so compiled variational quantum algorithms can be verified without symbolic reasoning.
  • The same trained discriminator can be reused across applications, and the generator can be optimized to match a reference circuit, giving a variational circuit-optimization loop that works directly on noisy hardware.
  • Because the test only misses real differences probabilistically and cannot fabricate differences, a detected mismatch is trustworthy under ideal operations; the residual risk is an undetected error, whose worst-case probability the paper bounds.
  • The architecture can plug into existing circuit-optimization tools as a hardware substitute for the classical simulation step that currently bottlenecks them.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Beyond the paper: the theoretical completeness is a continuum statement; any practical run uses finitely many product states and finitely many shots, so the true guarantee is statistical. A natural extension is a full false-negative analysis as a function of the number of input states, the shot count, and the error's subspace dimension.
  • Beyond the paper: the local random circuit produces only product states, so it may be a weaker probe for errors concentrated on entangled subspaces. One could test whether inserting a few entangling layers into the random module improves worst-case detection at modest depth.
  • Beyond the paper: because the discriminator is trained on the same hardware that later runs the verification, the method's reliability is coupled to the noise it is meant to detect. An experiment with deliberately injected coherent errors of varying strength would map the smallest detectable error for a given shot budget.
  • Beyond the paper: collecting output fidelities over a tomographically complete set of inputs could turn the framework from a pass/fail checker into a characterization tool that reconstructs the difference matrix $D$, giving more information than equivalence alone.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes the RH architecture, which prepends two identical random circuits to the EQ-GAN framework to extend it from quantum state learning to unitary transformation learning. The authors claim a theoretical completeness proof (Theorem 1), introduce an efficient local random circuit, and demonstrate three applications—equivalence checking of non-parameterized circuits, equivalence checking of parameterized circuits, and variational circuit reconstruction—through classical simulation and experiments on the Zuchongzhi-2 processor, including benchmarks on VeriQBench circuits up to 9 qubits.

Significance. If the completeness claim were rigorously established, the RH architecture would offer a hardware-based alternative to classical simulation for circuit equivalence checking, with potential scalability to large circuits. The paper's empirical demonstrations on 4–9 qubits show clean separation between equivalent and non-equivalent circuits for typical cases, and the open-source code and real-hardware experiments are valuable assets. However, the theoretical completeness as stated is not established: the proof of Theorem 1 contains an invalid step, and the paper's own worst-case analysis shows an exponentially small detection probability for certain errors. The idea is promising as a variational heuristic, but the central 'large-scale complete' claim requires a substantially stronger finite-sample analysis or a deliberate weakening of the claim.

major comments (3)
  1. [Section 3.2, Theorem 1 (Eq. (6))] The proof of Theorem 1 is not valid. From Eqs. (5) and (6), the fact that D|φ⟩ = |φ⟩ for a particular |φ⟩ does not imply that each side of Eq. (6) vanishes; the components of a random state are not independent in the sense of arbitrary variation, and the phrase 'mutually independent components' has no rigorous meaning for a fixed, normalized vector. The theorem as stated—if D|φ⟩ = |φ⟩ for every |φ⟩—is true, but the proof does not establish it. More importantly, the application uses only finitely many sampled states, and the paper provides no finite-sample bound relating the observed pfailure to a bound on the difference matrix D. The subsequent sentence that the probability of non-equivalence is 'statistically zero' is therefore unsupported by the presented argument.
  2. [Section 3.3, Eq. (7)] The local random circuit generates product states whose 2^n computational-basis amplitudes are functions of only 2n independent random parameters; these amplitudes are not 'mutually independent' as claimed in the text. The set of product states is a measure-zero subset of the Hilbert space, so the premise of Theorem 1—'arbitrary random state'—is not satisfied. Even in an infinite-sample limit, the paper's own worst-case analysis in Section 3.2 with D = I^{⊕(n-1)} ⊕ U_s gives an undetected-error probability of e^{-m/2^{n-1}} for m measurement shots. For n = 20 and m = 1000, this is approximately 99.8%, so the Abstract's claim of a 'large-scale complete' architecture is not supported by the provided analysis.
  3. [Section 4 and Appendix A.2 (Table 2)] The experimental benchmark is encouraging but only demonstrates separation for circuits of 4–9 qubits with errors that are single-qubit rotations (Ry(δ), Rx(1.23)) or simple gate insertions. These errors induce typical fidelity reductions that a few hundred shots can detect; the worst-case errors identified in Section 3.2 are not included in the benchmark. Without a finite-sample completeness bound, the empirical results cannot support the claim that the architecture is a complete verification method at scale. This is not a criticism of the heuristic utility, but the manuscript's central claim must be either proven with rigorous sample complexity or explicitly reframed as a heuristic.
minor comments (5)
  1. [Section 4.1] The text reports initial and final pfailure values (3.148 × 10^-4 decreasing to 2.232 × 10^-17) that are inconsistent with Table 1, which lists 1.291 × 10^-3 and 1.214 × 10^-9 for the same quantities; the authors should reconcile these numbers.
  2. [Figure 5 caption] The caption contains a typo: 'Refence' should be 'Reference'.
  3. [Section 2.2] The term 'SW AP' appears with a spurious space in several places (e.g., 'SW AP test'); it should be 'SWAP test'.
  4. [Eq. (7)] The notation bin(i)_k is undefined; it presumably denotes the k-th bit of the binary representation of i, but this should be stated explicitly.
  5. [Table 2] The pfailure_Y values around 10^-31 are floating-point artifacts of exact simulation and should be reported as exactly zero, with a note that the nonzero values arise from numerical precision; otherwise readers may misinterpret machine precision as a physical detection limit.

Circularity Check

0 steps flagged · score 1.0 of 10

No circular derivation found; the RH architecture is validated on external benchmarks, and the completeness theorem, though statistically overstated for finite shots, is not derived from its own conclusion.

full rationale

The paper's central claim is that prepending identical random circuits to EQ-GAN turns state learning into unitary learning. The load-bearing step is Theorem 1, which infers D=I from D|φ⟩=|φ⟩ for arbitrary random states. That inference is a standard spanning argument; the proof's independence step is compressed but not circular, because varying the independent component forces the coefficients to vanish. The finite-sample version is not established: the paper's own worst-case analysis gives undetected-error probability e^{-m/2^{n-1}}, so 'statistically zero' overstates what Theorem 1 proves. That is a statistical and correctness gap, not a reduction of the conclusion to the input. Similarly, the local random circuit is asserted, not proven, to satisfy the theorem's independence premise; this is an unsupported assumption rather than a circular definition. The experimental validation uses external VeriQBench circuits and analytic δ-distortion cases, with no fitted parameter renamed as a prediction. Self-citations to VeriQBench, MindSpore Quantum, and earlier He et al. papers are present but are not load-bearing: the benchmark supplies external test circuits, the software citation does not justify the theoretical claim, and the earlier papers are used only for motivational context. Accordingly, no circular step is exhibited, and the score reflects only minor non-load-bearing self-citation.

Assumptions & free parameters 0 free parameters · 6 assumptions · 0 invented entities

The central claim rests on standard quantum mechanics, the SWAP-test fidelity relation, the EQ-GAN noise-compensation assumption, and the probabilistic completeness of finite random-state testing. No constants are fitted to make the results match; the discriminator and generator parameters are learned as part of the algorithm.

assumptions (6)
  • standard math Standard quantum mechanics: state vectors, unitary gates, Born rule measurement probabilities.
    Used throughout for the SWAP test relation (Eq. 1-2) and for the difference matrix D = U†U′ in Section 3.2.
  • standard math The destructive SWAP test probability relation pfailure = 1 - |⟨ϕ|ψ⟩|².
    Eq. (2), from Garcia-Escartin and Chamorro-Posada; basis for all test-failure cost functions.
  • domain assumption The parameterized discriminator trained on |0⟩ states can perfectly compensate coherent CZ errors for all input states.
    Section 3.1 and preliminary experiment; inherited from EQ-GAN Niu et al. 2022. Assumes the coherent error model is a set of Rz gates after each CZ.
  • domain assumption Random product states generated by the local circuit are a complete probe: matching them implies U = U′.
    Sections 3.2-3.3; relies on amplitudes being mutually independent and on the tested states spanning the unitary. The paper's own worst-case detection bound e^{-m/2^{n-1}} shows the finite-sample version can be exponentially weak.
  • domain assumption The no-false-positive claim assumes ideal operations and perfect measurements.
    Stated in Section 3.2: 'assuming ideal operations and perfect measurements in experiment.' Hardware results show nonzero pfailure for equivalent circuits, so this assumption is violated in practice.
  • domain assumption The coherent-error noise model used in simulation (Rz gates with σ = 0.02) represents real hardware errors.
    Preliminary experiment, Section 4.1; used to train and evaluate the discriminator's robustness.

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Cite this review

Pith. "Pith review of RH: An Architecture for Redesigning Quantum Circuits on Quantum Hardware Devices." pith.science (2026). https://pith.science/paper/YXORZBAB

@misc{pith2026241220893,
  author       = {Pith},
  title        = {Pith review of: RH: An Architecture for Redesigning Quantum Circuits on Quantum Hardware Devices},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/YXORZBAB}},
  note         = {Machine review of arXiv:2412.20893}
}
read the original abstract

In this paper we present an architecture that enables the redesign of large-scale quantum circuits on quantum hardware based on the entangling quantum generative adversarial network (EQ-GAN). Specifically, by prepending a random quantum circuit module to the standard EQ-GAN framework, we extend its capability from quantum state learning to unitary transformation learning. The completeness of this architecture is theoretically proved. Moreover, an efficient local random circuit is proposed, which significantly enhances the practicality of our architecture. For concreteness, we apply this architecture to three crucial applications in circuit optimization, including the equivalence checking of (non-) parameterized circuits, as well as the variational reconstruction of quantum circuits. The feasibility of our approach is demonstrated by excellent results in both classical and noisy intermediate-scale quantum (NISQ) hardware implementations. We believe our work will facilitate the implementation and validation of the advantages of quantum algorithms.

Figures

Figures reproduced from arXiv: 2412.20893 by the authors.

Figure 3
Figure 3. The schematic diagram of the RH architecture. [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. The local random circuit used in this paper. [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. (a) A two-qubit phase-flipper circuit for basis states [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figures from the paper (2 more)
Figure 6
Figure 6. Figure 6: (a) The probabilities of test failure as functions of steps in training the discriminator [PITH_FULL_IMAGE:figures/full_fig_p008_6.png]
Figure 7
Figure 7. Figure 7: The mapping schematic between the logical qubits and the physical qubits arranged [PITH_FULL_IMAGE:figures/full_fig_p013_7.png]

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Reference graph

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