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REVIEW 4 major objections 5 minor 44 references

Digitally Mutating NV-FPGAs into Physically Clone-Resistant Units

T0 review · 4 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read The paper claims that future non-volatile FPGAs can make themselves clone-resistant by self-mutating a pre-compiled cipher template into a per-device Secret Unknown Cipher, with two proposed cipher classes of $2^{1350}$ and $2^{1234}$…

desk verdict A genuine new cipher-class proposal with honest admissions, but the paper's central claim of demonstrating self-mutating bitstream feasibility is not supported by the experiments. read the letter →

arxiv 1908.03898 v1 pith:Z4WA6CND submitted 2019-08-11 cs.CR

Ayoub Mars , Wael Adi This is my paper · ORCID
classification cs.CR
keywords secretunknowncipherphysicallyunclonablefunctionFPGAbitstreammanipulationnon-volatileself-reconfigurationcloneresistanceSPNblocktruerandomnumbergenerator
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a non-volatile FPGA can be made physically clone-resistant by having it create its own Secret Unknown Cipher (SUC): a device-internal random selection from a cipher class so large that the resulting cipher is unknown even to its designer. The mechanism is a pre-compiled cipher-layout template inside the configuration bitstream, plus a mutation generator that rewrites only template bits under the control of the FPGA's true random number generator, then deletes itself and locks the device irreversibly. Two concrete cipher families are designed to fit FPGA LUT resources: a non-involutive class with $2^{1350}$ members and an involutive class with $2^{1234}$ members. If the mechanism worked, SUCs would give each device a consistent digital identity, replacing analog PUFs without error-correction hardware. The paper prototypes the cipher logic on a commercial non-volatile SoC FPGA, while admitting that the self-mutation infrastructure itself does not yet exist in any commercial device.

What carries the argument

The object that carries the argument is the cipher-layout template together with a bitstream manipulator called the GENIE. The template is a block of free FPGA fabric and non-volatile memory wired into the normal application bitstream with harmless default contents; because its positions are known at compile time, the GENIE can overwrite only those bits while the bitstream is being decrypted and loaded, selecting S-boxes and key-schedule LUT contents according to true random bits. After one use, the GENIE is deleted and the device is irreversibly locked, so the resulting Secret Unknown Cipher is permanent, unobservable, and not reproducible. The two proposed template structures, NI-SUC and I-SUC, are substitution-permutation block ciphers whose component mappings (optimal 4-bit S-boxes, involutive S-boxes, fixed or involutive diffusion permutations, and LUT-based random key schedules) are chosen precisely because they map one-to-one onto FPGA LUT configuration bits.

What would settle it

A reader can test the central claim on current silicon by loading the proposed encrypted template bitstream into an unmodified non-volatile SoC FPGA and attempting the GENIE's decrypt, rewrite, and lock sequence; the device does not expose the clear bitstream or template bit positions, so the sequence cannot complete. If, on any modified device, reloading the original encrypted bitstream or reading back the configuration restores the pre-mutation state, the irreversible-unknown property fails and the unit would be cloneable.

Watch

Extended reading notes

Core claim

Secret Unknown Ciphers are presented as practically creatable: a non-volatile SoC FPGA can hold a pre-compiled cipher-layout template and, during enrollment, modify only the template's configuration bits under the control of its internal true random number generator, thereby committing each device to one unknown cipher selected from a class so large that neither the designer, the manufacturer, nor the trusted authority can know or reproduce it. The paper proposes two concrete template families adapted to FPGA LUT resources: NI-SUC, a 31-round substitution-permutation network with 16 optimal 4-bit S-boxes and 32 random round keys stored in 64 LUTs, giving $2^{1350}$ possible ciphers; and I-SUC, a 32-round involutive SPN with involutive S-boxes and a fixed involutive diffusion layer, giving $2^{1234}$ possible ciphers. It reports prototypes of both cipher cores in a real SoC FPGA technology, with about 212 to 226 LUTs and 72 flip-flops and 896 to 1152 bytes of software overhead, and argues that avalanche behavior becomes near-ideal within a few rounds and that linear and differential attacks require more than $2^{120}$ chosen plaintexts. The central conclusion is that digital, consistent, clone-resistant identities are feasible at low cost, with the acknowledged caveat that the self-mutating bitstream infrastructure requires FPGA vendor changes that do not yet exist.

Load-bearing premise

The construction assumes a non-volatile FPGA that can decrypt its own bitstream internally, rewrite template bits under true-random control, and then irreversibly lock itself and erase all trace of the process; the paper states that no such commercial device exists today and that the closest vendor technology would require modified bitstream management.

Editorial extensions

If this is right

  • If the required non-volatile FPGA infrastructure appears, each unit gets a unique permanent cipher chosen from $2^{1350}$ or $2^{1234}$ possibilities, making identical devices overwhelmingly unlikely.
  • Because the cipher is digital and permanently locked, identity verification becomes repeatable without fuzzy extractors: a challenge-response pair authenticates the unit, then is consumed as a one-time ticket.
  • The prototyped cores cost about 212 to 226 LUTs and 72 flip-flops, with 896 to 1152 bytes of software overhead, so the identity module could fit into otherwise free FPGA fabric.
  • The security analysis implies that classical linear and differential attacks need more than $2^{120}$ chosen plaintexts, and Grover-style quantum search still leaves roughly $2^{137}$ to $2^{163}$ operations of work.
  • Because the GENIE is deleted and the design locked, the trusted authority cannot recreate or share the cipher, shifting clone-resistance from the manufacturer to the end user.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: The same template-mutation mechanism, if built, would generalize to unknown hash functions and stream ciphers, since the only real requirements are known template bit locations and TRNG-controlled LUT contents.
  • Editorial inference: The actual engineering bottleneck is vendor bitstream management; a public proof of concept would need an FPGA that exposes template bit addresses to an on-chip GENIE and then irreversibly blocks readback, a feature currently absent from commercial parts.
  • Editorial inference: A natural testable extension is to simulate the full mutation loop on a model FPGA bitstream, feed it many TRNG streams, and verify that the resulting cipher instances are distinct, avalanche-sound, and unrecoverable from the final locked state.
  • Editorial inference: The one-time-ticket protocol implies that an enrolled device cannot be re-enrolled after the GENIE is deleted, which could make SUCs useful for anti-counterfeiting and secure software-update chains, not just identification.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes a technique for creating Secret Unknown Ciphers (SUCs) inside non-volatile SoC FPGAs by manipulating an encrypted configuration bitstream on-chip under TRNG control. It introduces two cipher classes, NI-SUC and I-SUC, with claimed class sizes of about 2^1350 and 2^1234, reports hardware and software complexity measurements from a SmartFusion2 prototype, and gives security analyses covering linear, differential, and post-quantum attacks. The stated main contribution is to show the feasibility of self-mutating unknown cipher modules in a non-volatile FPGA environment as a digital replacement for analog PUFs.

Significance. If the self-mutation process were actually realizable, SUCs could offer a useful digital alternative to analog PUFs, avoiding fuzzy extractors and operational inconsistency. The manuscript makes some constructive contributions: it gives concrete cipher-template designs, the class-size arithmetic is straightforward, and the reported resource usage for the static ciphers is low. However, the central feasibility claim is not demonstrated by the prototype, and the security claims largely reduce to class-size entropy rather than validated attack complexity. The paper is therefore more a concept proposal than a demonstrated feasibility result, and its significance as a research contribution is substantially lower than claimed.

major comments (4)
  1. [I and V.C, Fig. 5] The abstract's central claim, 'to show the feasibility of self-mutating unknown cipher-modules,' is not supported by the reported experimental work. Section I explicitly concedes that 'FPGA fabrics allowing even the proposed approach do not contemporarily exist,' and Section V.C states that Microsemi's bitstream management 'requires to be modified' to allow bitstream manipulation, to reveal template bit locations, and to enable the one-way lock. The SmartFusion2 measurements in Tables II and III implement only the static NI-SUC and I-SUC encryption/decryption logic; the GENIE, the internal decryption of EBS' to BS', the on-the-fly bitstream manipulation, and the irreversible lock are neither implemented nor measured. Thus the prototype supports the cipher templates but not the mutation process that is the stated main contribution.
  2. [II.C and VI.E/VII.F] The security level is defined as CRE = log2 S and then reported as the achieved security, e.g., 'cloning resistance entropy of 1350 bits' in Section VI.E and the post-quantum attack complexities in Section VIII.C. This is circular: it assumes that an attacker's effort equals exhaustive search over the cipher class S, but no argument is given that recovering a specific instance from challenge-response pairs requires that search. The class-size arithmetic is internally consistent, but it does not, by itself, establish a security level against linear, differential, algebraic, or structural attacks; the separate cryptanalysis in Section VIII does not close this gap.
  3. [VIII.A-B] The linear and differential cryptanalysis sections do not substantiate the claimed 'at least 2^120' data complexity for ciphers with 30 or more rounds. The paper cites Biryukov-Shamir and Borghoff et al. structural attacks on ciphers with secret S-boxes ([33]–[36]) but does not analyze whether those techniques apply to the proposed 31-round NI-SUC and 32-round I-SUC constructions. The Lemmas only give minimum active S-box counts for two-round trails; they are not accompanied by a full characteristic over the whole cipher or by an analysis of the S-box-recovery step that the paper itself acknowledges is necessary. The security bound is therefore not demonstrated.
  4. [VIII.C] The post-quantum bounds of O(2^137) and O(2^163) are obtained by taking square roots of the S-box class sizes (2^274 and 2^326) and applying Grover's algorithm. This again equates class size with attack complexity. The presentation is also ambiguous: the text says the effective attack complexity is computed 'without considering the cardinality of the key scheduling for NI-SUC,' but the relationship of these numbers to the total reported class sizes (2^1350 and 2^1234) is not explained. No quantum attack model is given in which the class-search predicate can be evaluated efficiently, so these figures should not be presented as proven security levels.
minor comments (5)
  1. [VI.A, VI.E, VII.F] The displayed equations for the class cardinalities, especially equations (6) and (16), are garbled in the text and should be rewritten in a standard, unambiguous form.
  2. [VI.B and VII.B] The numerical approximations '20.41 032 2396' and '17.151 20 245 9' appear corrupted; they should be replaced by clear decimal values or exact integers.
  3. [Fig. 6] Figure 6 contains many stray 'X' characters that obscure the intended bitstream representation and should be redrawn.
  4. [References] Reference [41] is incomplete and incorrectly formatted; it should cite P. W. Shor, 'Algorithms for quantum computation: discrete logarithms and factoring,' FOCS 1994.
  5. [VIII.D] The avalanche statistics are based on 1,000 SUC instances and 100 messages per instance, but no confidence intervals are provided; this is acceptable as an illustration but not as a statistical validation.

Circularity Check

1 steps flagged · score 4.0 of 10

Security-level claims are definitional restatements of the cipher-class size, while the cipher design and future-FPGA feasibility discussion retain independent content.

  1. self definitional [Section II.C; Section VI.F; Section VII.F]
    "The Cloning Resistance Entropy (CRE) for a SUC can be defined as: SUC-Cloning-Resistance-Entropy CRE= log2 S ... A single unknown choice out of this huge number of ciphers can be considered as a practically unknown cipher with a cloning resistance entropy of 1350 bits."

    The paper defines the security metric as the logarithm of the cipher-class size S, then reports the 'cloning resistance entropy' as exactly log2 of the class sizes computed for the two designs (1350 and 1234 bits). This is not an independent bound derived from cryptanalysis; it is the entropy of the random-selection input (S-box choices plus key-schedule LUT contents) restated as a security level. The post-quantum figures (O(2^137) and O(2^163)) are the Grover square roots of the same class-size input. Thus the headline security level reduces, by definition, to the design parameter S.

full rationale

The derivation of the two cipher classes is self-contained: each class size is counted from independent S-box choices and LUT-based key-schedule bits, and the avalanche, linear, and differential bounds follow from quoted external S-box classifications and the invoked permutation properties; no fitted data are used. The only genuine circularity is definitional: CRE is defined as log2 S, and the same quantity is then announced as the achieved 'cloning-resistance-entropy' (1350/1234 bits), so the security headline restates the input entropy rather than an independent cryptanalytic result. The post-quantum attack-complexity is likewise a Grover square root of this class size. The paper itself flags the central feasibility limitation, stating that 'FPGA fabrics allowing even the proposed approach do not contemporarily exist' (Section I) and that Microsemi bitstream management 'requires to be modified' (Section V.C), so the reported prototype covers only static cipher logic rather than the mutation process; this is a feasibility/correctness gap, not a circularity. Overall, the central future-hardware concept and the cipher constructions retain independent content, so the circularity is partial and confined to the security-level metric.

Assumptions & free parameters 2 free parameters · 6 assumptions · 2 invented entities

The paper introduces no fitted physical constants, but it relies on hand-chosen round counts and on an assumed future FPGA capability. The central security quantity, CRE, is defined as the class size and then used as the attack complexity, which is the main circular element.

free parameters (2)
  • Round count R for NI-SUC = 31
    Chosen by the authors to push estimated linear and differential data complexity beyond 2^120; no optimization or security proof fixes it.
  • Round count R for I-SUC = 32
    Same hand choice for the involutive variant; the avalanche simulation shows saturation at 3 to 7 rounds, so the round counts are safety margins, not derived from a formal bound.
assumptions (6)
  • domain assumption Future non-volatile FPGAs will support internal self-reconfiguration, bitstream manipulation, and irreversible locking.
    The entire creation process depends on this; the paper states the technology does not yet exist (Section IV.E, V.C).
  • domain assumption The TRNG output is unpredictable and unobservable, and GENIE deletion is irreversible.
    Required for the created cipher to be unknown to the designer and manufacturer (Section II.B, IV.C).
  • ad hoc to paper Cloning resistance entropy CRE = log2 S is a valid measure of attack complexity for an unknown cipher.
    This is the paper's definition (Section II.C), not a derived security bound; it ignores structural attacks.
  • standard math The counts of optimal 4-bit S-boxes (2^20.4) and involutive optimal S-boxes (2^17.15) from [30][31] are correct.
    The class cardinalities and security entropies depend on these externally classified counts.
  • domain assumption Invasive attacks on future locked 3D or memristor structures are practically infeasible.
    Used to justify permanent unclonability (Section II.D).
  • domain assumption Linear and differential active-S-box lower bounds for two rounds extrapolate to the full 31 or 32 round ciphers with independent round keys.
    The lemmas count active S-boxes in two rounds; no full-round trail analysis or key-schedule interaction is given (Section VIII.A-B).
invented entities (2)
  • Secret Unknown Cipher (SUC)
    purpose: Device-specific unknown cipher used as a clone-resistant physical identity
    Conceptual primitive introduced by the authors; no external measurement or falsifiable prediction beyond the class-size counts.
  • GENIE mutation generator
    purpose: One-time internal bitstream manipulator that installs the random cipher and is then deleted
    Described but not implemented; depends on nonexistent FPGA infrastructure.

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Cite this review

Pith. "Pith review of Digitally Mutating NV-FPGAs into Physically Clone-Resistant Units." pith.science (2026). https://pith.science/paper/Z4WA6CND

@misc{pith2026190803898,
  author       = {Pith},
  title        = {Pith review of: Digitally Mutating NV-FPGAs into Physically Clone-Resistant Units},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/Z4WA6CND}},
  note         = {Machine review of arXiv:1908.03898}
}
abstract

The concept of Secret Unknown Ciphers (SUCs) was introduced a decade ago as a new visionary concept without devising practical real-world examples. The major contribution of this work is to show the feasibility of "self-mutating" unknown cipher-modules for physical security applications in a non-volatile FPGA environment. The mutated devices may then serve as clone-resistant physical units. The mutated unpredictable physical-digital modules represent consistent and low-cost physical identity alternatives to the traditional analog Physically Unclonable Functions (PUFs). PUFs were introduced two decades ago as unclonable analog physical identities which are relatively complex and suffer from operational inconsistencies. We present a novel and practical SUC-creation technique based on pre-compiled cipher-layout-templates in FPGAs. A devised bitstream-manipulator serves as "mutation generator" to randomly-manipulate the bitstream without violating the FPGA design rules. Two large cipher classes (class-size larger than $2^{1000}$) are proposed with optimally designed structure for a non-volatile FPGA fabric structure. The cipher-mutation process is just a simple random unknown-cipher-selection by consulting the FPGA's internal True Random Number Generator (TRNG). The security levels and qualities of the proposed ciphers are evaluated. The attained security levels are scalable and even adaptable to the post-quantum cryptography. The hardware and software complexities of the created SUCs are experimentally prototyped in a real field FPGA technology to show very promising results.

Discussion (0). Continue with ORCID to comment.

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Pith tools

Reviewed August 14, 2026 · model on record in the stance chip above.