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arxiv: 1802.09517 · v1 · pith:ZNK2UTBPnew · submitted 2018-02-26 · 💻 cs.CR · cs.AR· cs.PL

Memory Tagging and how it improves C/C++ memory safety

classification 💻 cs.CR cs.ARcs.PL
keywords memorytaggingsafetyhardwareimplementationsimproveaarch64basic
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Memory safety in C and C++ remains largely unresolved. A technique usually called "memory tagging" may dramatically improve the situation if implemented in hardware with reasonable overhead. This paper describes two existing implementations of memory tagging: one is the full hardware implementation in SPARC; the other is a partially hardware-assisted compiler-based tool for AArch64. We describe the basic idea, evaluate the two implementations, and explain how they improve memory safety. This paper is intended to initiate a wider discussion of memory tagging and to motivate the CPU and OS vendors to add support for it in the near future.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Optimized Memory Tagging on AmpereOne Processors

    cs.AR 2025-11 unverdicted novelty 6.0

    AmpereOne implements MTE with zero tag-storage memory overhead and single-digit performance impact while identifying application memory management as the main remaining bottleneck.

  2. NanoTag: Systems Support for Efficient Byte-Granular Overflow Detection on ARM MTE

    cs.CR 2025-09 unverdicted novelty 6.0

    NanoTag enables byte-granular overflow detection on unmodified MTE binaries by combining hardware tagging with selective software tripwire checks on the Scudo allocator.