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High-throughput decoder of quasi-cyclic LDPC codes with limited precision for continuous-variable quantum key distribution systems

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arxiv 2207.01860 v1 pith:ZX2X2KML submitted 2022-07-05 quant-ph

classification quant-ph
keywords mbpsreal-timecv-qkddecoderratesecretsystemscontinuous-variable
verification ladder T0 review T1 audit T2 compute T3 formal
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More than Mbps secret key rate was demonstrated for continuous-variable quantum key distribution (CV-QKD) systems, but real-time postprocessing is not allowed, which is restricted by the throughput of the error correction decoding in postprocessing. In this paper, a high-throughput FPGA-based quasi-cyclic LDPC decoder is proposed and implemented to support Mbps real-time secret key rate generation for CV-QKD for the first time. A residual bit error correction algorithm is used to solve the problem of high frame errors rate (FER) caused by the limited precision of the decoder. Specifically, real-time high-speed decoding for CV-QKD systems with typical code rates 0.2 and 0.1 is implemented on a commercial FPGA, and two throughputs of 360.92Mbps and 194.65Mbps are achieved, respectively, which can support 17.97 Mbps and 2.48 Mbps real-time generation of secret key rates under typical transmission distances of 25km and 50km, correspondingly. The proposed method paves the way for high-rate real-time CV-QKD deployment in secure metropolitan area network.

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  1. Fixed Point Exploration For CV-QKD IR QC-MET-LDPC Toward Hardware Implementation

    cs.AR 2026-07 conditional novelty 4.0 of 10

    For a low-rate MET-LDPC code at very low SNR, SPA decoding is most robust to fixed-point precision, and Q8.4 is the practical hardware-efficient choice for SPA.

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