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Donghyuk Lee

Identifiers

  • name variant Donghyuk Lee 0.60 · backfill

Papers (22)

  1. What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study cs.AR · 2018 · author #4
  2. Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency cs.AR · 2018 · author #5
  3. SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure cs.AR · 2018 · author #7
  4. LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency cs.AR · 2018 · author #4
  5. Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency cs.AR · 2018 · author #7
  6. Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips cs.AR · 2018 · author #6
  7. RowClone: Accelerating Data Movement and Initialization Using DRAM cs.AR · 2018 · author #4
  8. Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism cs.AR · 2018 · author #3
  9. Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost cs.AR · 2018 · author #1
  10. Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins cs.AR · 2018 · author #1
  11. Improving DRAM Performance by Parallelizing Refreshes with Accesses cs.AR · 2017 · author #2
  12. GRIM-filter: fast seed filtering in read mapping using emerging memory technologies q-bio.GN · 2017 · author #4
  13. Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms cs.AR · 2017 · author #7
  14. Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM cs.AR · 2016 · author #2
  15. Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips cs.AR · 2016 · author #1
  16. Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity cs.AR · 2016 · author #1
  17. Adaptive-Latency DRAM (AL-DRAM) cs.AR · 2016 · author #1
  18. RowHammer: Reliability Analysis and Security Implications cs.DC · 2016 · author #6
  19. Tiered-Latency DRAM (TL-DRAM) cs.AR · 2016 · author #1
  20. Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses cs.AR · 2016 · author #2
  21. Simultaneous Multi Layer Access: A High Bandwidth and Low Cost 3D-Stacked Memory Interface cs.AR · 2015 · author #1
  22. The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity cs.DC · 2015 · author #2

Mentions

  • 1506.03160 #1 · backfill · confidence 0.70 Donghyuk Lee
  • 1504.00390 #2 · backfill · confidence 0.70 Donghyuk Lee

Frequent Coauthors