Lavanya Subramanian

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Papers (9)

1. Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems cs.AR · 2018 · author #1
2. Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost cs.AR · 2018 · author #5
3. High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems cs.AR · 2018 · author #3
4. Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips cs.AR · 2016 · author #3
5. Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism cs.AR · 2016 · author #8
6. Tiered-Latency DRAM (TL-DRAM) cs.AR · 2016 · author #5
7. Providing High and Controllable Performance in Multicore Systems Through Shared Resource Management cs.DC · 2015 · author #1
8. SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators cs.AR · 2015 · author #2
9. The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity cs.DC · 2015 · author #1

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Frequent Coauthors

• Onur Mutlu 8 shared papers
• Vivek Seshadri 5 shared papers
• Donghyuk Lee 4 shared papers
• Yoongu Kim 3 shared papers
• Gabriel H. Loh 2 shared papers
• Jamie Liu 2 shared papers
• Kevin Chang 2 shared papers
• Rachata Ausavarungnirun 2 shared papers
• Ben Jaiyen 1 shared papers
• Gennady Pekhimenko 1 shared papers
• Harsha Rastogi 1 shared papers
• Hiroyuki Usui 1 shared papers
• Kevin K. Chang 1 shared papers
• Lisa Hsu 1 shared papers
• Mike O'Connor 1 shared papers
• Mithuna Thottethodi 1 shared papers
• Samira Khan 1 shared papers
• Saugata Ghose 1 shared papers
• Srilatha Manne 1 shared papers
• Yasuko Eckert 1 shared papers