Barbell codes are a family of qLDPC codes with a matching superconducting chip layout enabling constant hardware complexity, simulated to preserve logical information over trillions of QEC cycles at 10^{-4} physical noise with under 30 data qubits per logical qubit.
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Clifford-deformed zero-rate LDPC codes achieve code-capacity thresholds approaching 50% under i.i.d. pure dephasing when the number of biased logical operators scales slower than distance or overlaps satisfy stated conditions, with new examples from tile codes.
A resource-reusing FPGA architecture for GARI-structured message-passing decoding of quantum LDPC codes with correlated errors achieves 596 ns average latency and 6x lower resource use than prior GARI hardware on a VCU19P device.
Local syndrome-based preprocessing accelerates BP decoders for quantum LDPC codes, delivering up to 10x speedup on the [[144,12,12]] code while maintaining or improving logical error rates.
Introduces a gauging-based method for fault-tolerant logical measurement achieving qubit overhead linear in operator weight up to polylog factors, adaptable to arbitrary codes.
A topical review unifying statistical mechanics, tensor network, and AI approaches to approximate maximum likelihood decoding for quantum error correction codes.
citing papers explorer
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Barbell Codes: qLDPC Codes for Superconducting Quantum Hardware
Barbell codes are a family of qLDPC codes with a matching superconducting chip layout enabling constant hardware complexity, simulated to preserve logical information over trillions of QEC cycles at 10^{-4} physical noise with under 30 data qubits per logical qubit.
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Clifford-deformed zero-rate LDPC codes with 50% biased noise thresholds
Clifford-deformed zero-rate LDPC codes achieve code-capacity thresholds approaching 50% under i.i.d. pure dephasing when the number of biased logical operators scales slower than distance or overlaps satisfy stated conditions, with new examples from tile codes.
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A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI
A resource-reusing FPGA architecture for GARI-structured message-passing decoding of quantum LDPC codes with correlated errors achieves 596 ns average latency and 6x lower resource use than prior GARI hardware on a VCU19P device.
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Accelerating BP-based decoders for QLDPC Codes with Local Syndrome-Based Preprocessing
Local syndrome-based preprocessing accelerates BP decoders for quantum LDPC codes, delivering up to 10x speedup on the [[144,12,12]] code while maintaining or improving logical error rates.
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Low-overhead fault-tolerant quantum computation by gauging logical operators
Introduces a gauging-based method for fault-tolerant logical measurement achieving qubit overhead linear in operator weight up to polylog factors, adaptable to arbitrary codes.
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Maximum Likelihood Decoding of Quantum Error Correction Codes
A topical review unifying statistical mechanics, tensor network, and AI approaches to approximate maximum likelihood decoding for quantum error correction codes.