SPARK is a sparsity-aware near-cache ILP accelerator achieving up to 15x performance and 152x energy reduction over CPUs for sparse ILPs on MIPLIB 2017 workloads.
Nem-gnn: Dac/adc-less, scalable, reconfigurable, graph and sparsity-aware near- memory accelerator for graph neural networks
4 Pith papers cite this work. Polarity classification is still indexing.
4
Pith papers citing it
fields
cs.AR 4years
2026 4representative citing papers
NEM-GNN proposes a scalable DAC/ADC-less PIM architecture for GNNs with early termination and CAR execution, claiming 80-230x performance and 850-1134x energy gains over prior accelerators.
SACHI reuses CPU L1 cache for all-digital Ising acceleration and reports 300x performance and 80x energy gains over BRIM on asset allocation, molecular dynamics, image segmentation, and TSP.
citing papers explorer
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A comprehensive study on ILP acceleration accounting for sparsity, area, energy, data movement using near-memory architecture
SPARK is a sparsity-aware near-cache ILP accelerator achieving up to 15x performance and 152x energy reduction over CPUs for sparse ILPs on MIPLIB 2017 workloads.
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A complete discussion on fully reconfigurable, digital, scalable, graph and sparsity-aware near-memory accelerator for graph neural networks
NEM-GNN proposes a scalable DAC/ADC-less PIM architecture for GNNs with early termination and CAR execution, claiming 80-230x performance and 850-1134x energy gains over prior accelerators.
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A detailed algorithmic study on a reuse-aware, near memory, all-digital Ising machine
SACHI reuses CPU L1 cache for all-digital Ising acceleration and reports 300x performance and 80x energy gains over BRIM on asset allocation, molecular dynamics, image segmentation, and TSP.
- A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM