Presents a coset ensemble decoder with algorithm-hardware co-design that claims better accuracy-latency trade-off and lower FPGA resource use than MWPM and UF baselines under depolarizing noise.
FPGA-Based Distributed Union-Find Decoder for Surface Codes,
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A pipelined framework with speculation for logical operations in fault-tolerant quantum computation reduces total pipeline steps by 20-40% on benchmarks by overlapping control, execution, and decoding stages.
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Stalls and Spequlation: Pipelined Execution for Fault Tolerant Quantum Computation
A pipelined framework with speculation for logical operations in fault-tolerant quantum computation reduces total pipeline steps by 20-40% on benchmarks by overlapping control, execution, and decoding stages.