A resource-reusing FPGA architecture for GARI-structured message-passing decoding of quantum LDPC codes with correlated errors achieves 596 ns average latency and 6x lower resource use than prior GARI hardware on a VCU19P device.
Title resolution pending
6 Pith papers cite this work. Polarity classification is still indexing.
6
Pith papers citing it
citation-role summary
background 2
other 1
citation-polarity summary
years
2026 6verdicts
UNVERDICTED 6representative citing papers
A new measurement schedule turns the heavy-hex subsystem code into the dynamic compass code, which demonstrates a threshold for stability and supports fault-tolerant lattice surgery.
Dynamic compass code on heavy-hex lattice yields competitive threshold and experimental 38.3% logical error rate improvement for distance-5 via ACES noise characterization and leakage-aware post-selection.
Bath memory reshapes transport patterns in the extended phase of the AAH transition but mainly renormalizes timescales in the localized phase.
A d_x2-y2 orbital bilayer t-J model with first-principles parameters unifies experimental Tc controls in La3Ni2O7 via particle-hole asymmetry and J_perp dependence, proposing electron doping to enhance Tc.
Neural networks learn via sparse retrospective updates triggered internally when prediction error exceeds a threshold derived from recent error statistics, leading to stepwise parameter changes in simulations.
citing papers explorer
-
Internally triggered retrospective learning in neural networks
Neural networks learn via sparse retrospective updates triggered internally when prediction error exceeds a threshold derived from recent error statistics, leading to stepwise parameter changes in simulations.