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Scalertl: Scaling llms with reasoning data and test-time compute for accurate rtl code generation,

3 Pith papers cite this work. Polarity classification is still indexing.

3 Pith papers citing it

fields

cs.AR 2 cs.PL 1

years

2026 3

verdicts

UNVERDICTED 3

representative citing papers

CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

cs.PL · 2026-06-04 · unverdicted · novelty 6.0

CASS-RTL identifies correctness-linked attention heads, builds a steering subspace from them, and applies a geometry-aware intervention that raises pass@1/5/10 accuracy 10-20% on VerilogEval and 5% on CVDP across multiple LLMs without retraining or extra labels.

Agentic Hardware Design as Repository-Level Code Evolution

cs.AR · 2026-06-26 · unverdicted · novelty 4.0

HORIZON applies repository-level self-evolution to hardware design artifacts and reports 100% completion on ChipBench, RTLLM, Verilog-Eval, and nine CVDP categories using a hands-free agent loop.

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