ChatSVA achieves 96.12% functional pass rate and 82.5% coverage in SVA generation on 24 RTL designs, delivering 33 percentage point gains and 11x better coverage than prior state-of-the-art.
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VeriGraphi introduces a knowledge-graph-anchored multi-agent pipeline that produces reliable hierarchical synthesizable Verilog for complex designs such as RISC-V processors.
SVA Generator improves semantic correctness of LLM-generated SystemVerilog Assertions by 22.7 percentage points on average for deeper properties using AST-grounded constraint injection and depth-stratified formal equivalence checking.
Aquas delivers a holistic hardware-software co-optimization framework on MLIR that models memory interfaces with cache effects and uses an e-graph retargetable compiler, achieving up to 15.61x speedup with 14.5% area overhead across four domains.
citing papers explorer
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ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
ChatSVA achieves 96.12% functional pass rate and 82.5% coverage in SVA generation on 24 RTL designs, delivering 33 percentage point gains and 11x better coverage than prior state-of-the-art.
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VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
VeriGraphi introduces a knowledge-graph-anchored multi-agent pipeline that produces reliable hierarchical synthesizable Verilog for complex designs such as RISC-V processors.
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Automated SVA Generation with LLMs
SVA Generator improves semantic correctness of LLM-generated SystemVerilog Assertions by 22.7 percentage points on average for deeper properties using AST-grounded constraint injection and depth-stratified formal equivalence checking.
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Aquas: Enhancing Domain Specialization through Holistic Hardware-Software Co-Optimization based on MLIR
Aquas delivers a holistic hardware-software co-optimization framework on MLIR that models memory interfaces with cache effects and uses an e-graph retargetable compiler, achieving up to 15.61x speedup with 14.5% area overhead across four domains.