HWE-Bench is the first repository-level benchmark for LLM agents on real hardware bug repair, where the best agent fixes 70.7% of 417 tasks but drops below 65% on complex SoC projects.
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Codev: Empowering llms for verilog generation through multi-level summarization
15 Pith papers cite this work. Polarity classification is still indexing.
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ChipCraftBrain achieves 97.2% pass rate on VerilogEval and 94.7% on CVDP benchmarks for generating functional RTL code using adaptive multi-agent orchestration and hybrid reasoning.
CHIA is a distributed graph-based framework for composing, deploying, and verifying agentic AI hardware/software co-design flows, demonstrated on RTL, simulation, and compiler tasks.
CASS-RTL identifies correctness-linked attention heads, builds a steering subspace from them, and applies a geometry-aware intervention that raises pass@1/5/10 accuracy 10-20% on VerilogEval and 5% on CVDP across multiple LLMs without retraining or extra labels.
Verilog-Evolve uses executable feedback from simulation, synthesis, timing, and GEMM metrics to refine LLM-generated Verilog and evolves skills across tasks, improving functional success and downstream hardware quality on VerilogEval and mixed-precision GEMM benchmarks.
RTL-BenchMT is an agent-assisted framework for dynamically maintaining RTL generation benchmarks by fixing flaws and reducing overfitting in LLM-based EDA applications.
Dr. RTL's multi-agent framework with group-relative skill learning achieves 21% WNS and 17% TNS timing improvements plus 6% area reduction on 20 real-world RTL designs over commercial synthesis tools.
VeriRAG is a RAG-based LLM framework that repairs Verilog RTL designs for DFT compliance using a curated dataset VeriDFT and achieves a 7.72-fold higher successful repair rate than zero-shot prompting.
ChipSeek is a hierarchical-reward reinforcement learning framework with Curriculum-Guided Dynamic Policy Optimization that integrates EDA simulator feedback to improve LLM-generated RTL code on both functional correctness and PPA metrics.
VeriPilot raises GPT-4o Verilog repair success from 54.3% to 85.71% on the CVDP benchmark by using golden-model semantic alignment and CDFG-based signal tracing.
ROSUM-MCTS applies MCTS-inspired hierarchical candidate expansion and a composite reward balancing functional correctness, local content adequacy, and fluency to improve LLM summaries of VHDL and Verilog code, outperforming baselines on eval datasets.
EstRTL improves correctness of generic-LLM RTL code generation by 3.2-9% via a Generation-Estimation-Correction loop that uses static functional scoring to decide acceptance, retry, or repair.
Using LLMs to encode logic condition tables into HDL code and decode back to tables mitigates hallucinations in hardware design automation.
StepPRM-RTL combines stepwise process-reward modeling, RAFT, and MCTS to fine-tune LLMs for RTL code, claiming over 10% gains in functional correctness on Verilog/VHDL benchmarks.
Empirical port of Gemma 4 31B LoRA training and vLLM inference from PyTorch/FSDP to JAX/Tunix shows TPU 1.61x faster training at 2.12x lower cost and superior long-context inference versus 2xH100 GPU.
citing papers explorer
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HWE-Bench: Benchmarking LLM Agents on Real-World Hardware Bug Repair Tasks
HWE-Bench is the first repository-level benchmark for LLM agents on real hardware bug repair, where the best agent fixes 70.7% of 417 tasks but drops below 65% on complex SoC projects.
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ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration
ChipCraftBrain achieves 97.2% pass rate on VerilogEval and 94.7% on CVDP benchmarks for generating functional RTL code using adaptive multi-agent orchestration and hybrid reasoning.
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CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
CHIA is a distributed graph-based framework for composing, deploying, and verifying agentic AI hardware/software co-design flows, demonstrated on RTL, simulation, and compiler tasks.
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CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
CASS-RTL identifies correctness-linked attention heads, builds a steering subspace from them, and applies a geometry-aware intervention that raises pass@1/5/10 accuracy 10-20% on VerilogEval and 5% on CVDP across multiple LLMs without retraining or extra labels.
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Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation
Verilog-Evolve uses executable feedback from simulation, synthesis, timing, and GEMM metrics to refine LLM-generated Verilog and evolves skills across tasks, improving functional success and downstream hardware quality on VerilogEval and mixed-precision GEMM benchmarks.
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RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
RTL-BenchMT is an agent-assisted framework for dynamically maintaining RTL generation benchmarks by fixing flaws and reducing overfitting in LLM-based EDA applications.
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Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
Dr. RTL's multi-agent framework with group-relative skill learning achieves 21% WNS and 17% TNS timing improvements plus 6% area reduction on 20 real-world RTL designs over commercial synthesis tools.
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VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
VeriRAG is a RAG-based LLM framework that repairs Verilog RTL designs for DFT compliance using a curated dataset VeriDFT and achieves a 7.72-fold higher successful repair rate than zero-shot prompting.
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ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
ChipSeek is a hierarchical-reward reinforcement learning framework with Curriculum-Guided Dynamic Policy Optimization that integrates EDA simulator feedback to improve LLM-generated RTL code on both functional correctness and PPA metrics.
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VeriPilot: An LLM-Powered Verilog Debugging Framework
VeriPilot raises GPT-4o Verilog repair success from 54.3% to 85.71% on the CVDP benchmark by using golden-model semantic alignment and CDFG-based signal tracing.
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ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards
ROSUM-MCTS applies MCTS-inspired hierarchical candidate expansion and a composite reward balancing functional correctness, local content adequacy, and fluency to improve LLM summaries of VHDL and Verilog code, outperforming baselines on eval datasets.
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EstRTL: Functional Estimation Guided RTL Code Generation
EstRTL improves correctness of generic-LLM RTL code generation by 3.2-9% via a Generation-Estimation-Correction loop that uses static functional scoring to decide acceptance, retry, or repair.
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Mitigating hallucinations and omissions in LLMs for invertible problems: An application to hardware logic design automation
Using LLMs to encode logic condition tables into HDL code and decode back to tables mitigates hallucinations in hardware design automation.
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StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis
StepPRM-RTL combines stepwise process-reward modeling, RAFT, and MCTS to fine-tune LLMs for RTL code, claiming over 10% gains in functional correctness on Verilog/VHDL benchmarks.
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Fine-Tuning and Serving Gemma 4 31B on Google Cloud TPU: A Technical Comparison with GPU Baselines
Empirical port of Gemma 4 31B LoRA training and vLLM inference from PyTorch/FSDP to JAX/Tunix shows TPU 1.61x faster training at 2.12x lower cost and superior long-context inference versus 2xH100 GPU.