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Hamiltonian Simulation Algorithms for Near-Term Quantum Hardware

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arxiv 2003.06886 v3 pith:O6XWBW5V submitted 2020-03-15 quant-ph

Hamiltonian Simulation Algorithms for Near-Term Quantum Hardware

classification quant-ph
keywords errormodelquantumhardwaresimulationcircuithamiltonianalgorithms
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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abstract

The quantum circuit model is the de-facto way of designing quantum algorithms. Yet any level of abstraction away from the underlying hardware incurs overhead. In the era of near-term, noisy, intermediate-scale quantum (NISQ) hardware with severely restricted resources, this overhead may be unjustifiable. In this work, we develop quantum algorithms for Hamiltonian simulation "one level below" the circuit model, exploiting the underlying control over qubit interactions available in principle in most quantum hardware implementations. We then analyse the impact of these techniques under the standard error model where errors occur per gate, and an error model with a constant error rate per unit time. To quantify the benefits of this approach, we apply it to a canonical example: time-dynamics simulation of the 2D spin Fermi-Hubbard model. We derive analytic circuit identities for efficiently synthesising multi-qubit evolutions from two-qubit interactions. Combined with new error bounds for Trotter product formulas tailored to the non-asymptotic regime and a careful analysis of error propagation under the aforementioned per-gate and per-time error models, we improve upon the previous best methods for Hamiltonian simulation by multiple orders of magnitude. By our calculations, for a 5$\mathbf\times$5 Fermi-Hubbard lattice we reduce the circuit depth from 800,160 to 1460 in the per-gate error model, or the circuit-depth-equivalent to 440 in the per-time error model. This brings Hamiltonian simulation, previously beyond reach of current hardware for non-trivial examples, significantly closer to being feasible in the NISQ era.

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