REVIEW
High-fidelity controlled-Z gate with maximal intermediate leakage operating at the speed limit in a superconducting quantum processor
Not yet reviewed by Pith; the record is open.
This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.
SPECIMEN: schema-true, not a live event
T0 review · schema-true
One-sentence machine reading of the paper's core claim.
pith:XXXXXXXX · record.json · timestamp
High-fidelity controlled-Z gate with maximal intermediate leakage operating at the speed limit in a superconducting quantum processor
read the original abstract
We introduce the sudden variant (SNZ) of the Net Zero scheme realizing controlled-$Z$ (CZ) gates by baseband flux control of transmon frequency. SNZ CZ gates operate at the speed limit of transverse coupling between computational and non-computational states by maximizing intermediate leakage. The key advantage of SNZ is tuneup simplicity, owing to the regular structure of conditional phase and leakage as a function of two control parameters. We realize SNZ CZ gates in a multi-transmon processor, achieving $99.93\pm0.24\%$ fidelity and $0.10\pm0.02\%$ leakage. SNZ is compatible with scalable schemes for quantum error correction and adaptable to generalized conditional-phase gates useful in intermediate-scale applications.
discussion (0)
Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.