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Scaling silicon-based quantum computing using CMOS technology: State-of-the-art, Challenges and Perspectives

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arxiv 2011.11753 v2 pith:OSF6QIDD submitted 2020-11-23 quant-ph cond-mat.mes-hall

classification quant-phcond-mat.mes-hall
keywords computingquantumcmosscalingtechnologychallengeperformancephysical
verification ladder T0 review T1 audit T2 compute T3 formal
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Complementary metal-oxide semiconductor (CMOS) technology has radically reshaped the world by taking humanity to the digital age. Cramming more transistors into the same physical space has enabled an exponential increase in computational performance, a strategy that has been recently hampered by the increasing complexity and cost of miniaturization. To continue achieving significant gains in computing performance, new computing paradigms, such as quantum computing, must be developed. However, finding the optimal physical system to process quantum information, and scale it up to the large number of qubits necessary to build a general-purpose quantum computer, remains a significant challenge. Recent breakthroughs in nanodevice engineering have shown that qubits can now be manufactured in a similar fashion to silicon field-effect transistors, opening an opportunity to leverage the know-how of the CMOS industry to address the scaling challenge. In this article, we focus on the analysis of the scaling prospects of quantum computing systems based on CMOS technology.

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