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NEO-QEC: Neural Network Enhanced Online Superconducting Decoder for Surface Codes
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Quantum error correction (QEC) is essential for quantum computing to mitigate the effect of errors on qubits, and surface code (SC) is one of the most promising QEC methods. Decoding SCs is the most computational expensive task in the control device of quantum computers (QCs), and many works focus on accurate decoding algorithms for SCs, including ones with neural networks (NNs). Practical QCs also require low-latency decoding because slow decoding leads to the accumulation of errors on qubits, resulting in logical failures. For QCs with superconducting qubits, a practical decoder must be very power-efficient in addition to having high accuracy and low latency. In order to reduce the hardware complexity of QC, we are supposed to decode SCs in a cryogenic environment with a limited power budget, where superconducting qubits operate. In this paper, we propose an NN-based accurate, fast, and low-power decoder capable of decoding SCs and lattice surgery (LS) operations with measurement errors on ancillary qubits. To achieve both accuracy and hardware efficiency of the SC decoder, we apply a binarized NN. We design a neural processing unit (NPU) for the decoder with SFQ-based digital circuits and evaluate it with a SPICE-level simulation. We evaluate the decoder performance by a quantum error simulator for the single logical qubit protection and the minimum operation of LS with code distances up to 13, and it achieves 2.5% and 1.0% accuracy thresholds, respectively.
Forward citations
Cited by 5 Pith papers
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High-Performance and Scalable Fault-Tolerant Quantum Computation with Lattice Surgery on a 2.5D Architecture
A sparse second qubit layer (Bypass) shortens lattice surgery paths, reducing decoding bottlenecks and enabling a 2.5D FTQC architecture that is faster and uses fewer resources in simulation.
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Machine Learning Decoding of Circuit-Level Noise for Bivariate Bicycle Codes
A recurrent transformer decoder trained on circuit-level noise beats BP-OSD on the [[72,12,6]] bivariate bicycle code in logical error rate and runtime consistency, but falls behind on the [[144,12,12]] code.
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Synchronization for Fault-Tolerant Quantum Computers
Active and Hybrid synchronization policies cut logical error rates by up to 2.4x and 3.4x compared to passive waiting, by distributing idle time across syndrome generation rounds.
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Surface-code Superconducting Quantum Processors: From Calibration To Logical Performance
A compilation of experiments showing that small surface codes on superconducting transmons can realize logical initialization, measurement, and gates, with fault-tolerant variants outperforming non-fault-tolerant ones...
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SOME: Symmetric One-Hot Matching Elector -- A Lightweight Microsecond Decoder for Quantum Error Correction
A QUBO-based decoder that reduces syndrome matching to one-hot permutation matrices is presented, but its headline claim of beating MWPM's threshold is not supported.
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