pith. sign in

arxiv: 2411.06376 · v3 · submitted 2024-11-10 · 💻 cs.LG · cs.AI· cs.AR

The Phantom of PCIe: Constraining Generative Artificial Intelligences for Practical Peripherals Trace Synthesizing

Zhibai Huang , Chen Chen , James Yen , Yihan Shen , Yongchen Xie , Zhixiang Wei , Kailiang Xu , Yun Wang
show 4 more authors
Fangxin Liu Tao Song Mingyuan Xia Zhengwei Qi
This is my paper

Pith reviewed 2026-05-23 16:59 UTC · model grok-4.3

classification 💻 cs.LG cs.AIcs.AR
keywords PCIeTLP tracesgenerative modelspost-processing filterdevice simulationprotocol constraintstrace synthesis
0
0 comments X

The pith

A post-processing filter applied after generative models produces valid large-scale PCIe TLP traces for device simulation.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper sets out to show that generative AI can synthesize realistic sequences of PCIe transaction packets if a dedicated filter removes outputs that break ordering, causality, and protocol rules. Hardware developers need such traces to run accurate simulations of new peripherals interacting with CPUs, yet raw generative outputs usually contain invalid packets that make the traces unusable. Phantom pairs any generative backbone with a custom filter that discards rule-breaking sequences while preserving enough statistical properties for downstream tasks. Experiments on traces from a real PCIe network interface card report large gains over unfiltered baselines.

Core claim

Phantom couples a generative backbone with a novel post-processing filter that enforces PCIe-specific constraints on ordering, causality, and protocol rules, thereby eliminating invalid TLP sequences. When applied to synthesize traces for an actual PCIe network interface card, the filtered outputs are practical at large scale and outperform backbone-only methods by up to 1000 times on task-specific metrics and up to 2.19 times on Fréchet Inception Distance.

What carries the argument

The post-processing filter that removes generated TLP sequences violating PCIe ordering, causality, and protocol rules.

If this is right

  • Device simulation workflows can replace limited real traces with much larger AI-generated sets.
  • New peripheral designs can be tested against realistic CPU interactions earlier in development.
  • Trace collection costs for validation drop because synthetic data scales without additional hardware captures.
  • Existing generative models for other interconnects become immediately usable once paired with analogous filters.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same filter-plus-generator pattern could be tested on other ordered bus protocols such as CXL or NVLink.
  • Integrating rule constraints directly into the generative sampling step might reduce the fraction of sequences discarded.
  • Synthetic traces produced this way could serve as training data for downstream tasks like traffic anomaly detection.

Load-bearing premise

The filter can enforce all relevant PCIe rules without discarding so much generated content that the surviving traces lose statistical fidelity or usefulness for device simulation.

What would settle it

Run the filtered traces in a cycle-accurate PCIe device simulator and measure whether the simulated device behavior matches the behavior produced by an equal volume of real captured traces; large divergence would falsify the claim.

Figures

Figures reproduced from arXiv: 2411.06376 by Chen Chen, Fangxin Liu, James Yen, Kailiang Xu, Mingyuan Xia, Tao Song, Yihan Shen, Yongchen Xie, Yun Wang, Zhengwei Qi, Zhibai Huang, Zhixiang Wei.

Figure 1
Figure 1. Figure 1: Topology of PCIe Devices in Modern Comput [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Overview of Tracyn. The architecture of Tracyn follows a [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Comparison of Raw Content, Prior Knowledge, [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: Improvements Attained from Tracyn’s Compo [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figure 4
Figure 4. Figure 4: Heatmap of Transmission Traffic Errors ( [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
read the original abstract

Peripheral Component Interconnect Express (PCIe) is the de facto interconnect standard for high-speed peripherals and CPUs. The development of PCIe devices for emerging applications requires realistic Transaction Layer Packet (TLP) traces that accurately simulate device-CPU interactions. While generative AI offers a promising avenue for synthesizing complex TLP sequences, it is prone to a critical challenge inherent in all generation tasks: hallucination. Naively applying these models often produces traces that violate fundamental PCIe protocol rules, such as ordering and causality, rendering them unusable for device simulation. To resolve this, our work introduces a methodology to bridge the gap between generative AI and high-fidelity device simulation. This paper presents Phantom, a framework that systematically addresses AI-generated hallucinations in TLP synthesis. Phantom achieves this by coupling a generative backbone with a novel post-processing filter that enforces PCIe-specific constraints, effectively eliminating invalid TLP sequences. We validate Phantom's effectiveness by synthesizing TLP traces for an actual PCIe network interface card. Experimental results show that Phantom produces practical, large-scale TLP traces, significantly outperforming existing models, with improvements of up to 1000$\times$ in task-specific metrics and up to 2.19$\times$ in Fr\'echet Inception Distance (FID) compared to backbone-only methods. The prototype implementation has been made open-source.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper introduces Phantom, a framework that pairs a generative AI backbone with a novel post-processing filter to synthesize valid PCIe Transaction Layer Packet (TLP) traces by enforcing protocol constraints such as ordering and causality. It validates the approach by generating traces for a real PCIe network interface card and reports up to 1000× gains in task-specific metrics and 2.19× improvement in Fréchet Inception Distance (FID) relative to backbone-only baselines, with the prototype released as open source.

Significance. If the central claims hold after proper validation of the filter, the work could offer a practical method for producing large-scale, protocol-compliant synthetic traces useful for PCIe device simulation and development. The open-source release supports reproducibility and is a clear strength.

major comments (2)
  1. [Abstract and §4] Abstract and §4 (Experimental Results): the headline performance claims (1000× task metrics, 2.19× FID) rest on the post-processing filter eliminating invalid sequences, yet no acceptance-rate statistics, before/after distribution comparisons, or ablation isolating the filter versus the backbone are supplied. Without these, it is impossible to rule out that reported gains arise from aggressive curation rather than improved generation.
  2. [§3] §3 (Methodology): the description of the novel filter states only that it 'eliminates invalid TLP sequences' without specifying the exact rules enforced, the fraction of outputs retained, or any proof that retained traces preserve the backbone model's statistical properties for downstream simulation utility.
minor comments (2)
  1. [Abstract] Abstract: the phrase 'up to 1000× in task-specific metrics' is vague without naming the metrics or the tasks; this should be clarified with concrete definitions.
  2. [§2] The manuscript would benefit from an explicit statement of the generative backbone architecture and training dataset details, which are referenced but not described in the provided abstract-level summary.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback. We address the two major comments below and will revise the manuscript accordingly to strengthen the presentation of the filter's role and validation.

read point-by-point responses

  1. Referee: [Abstract and §4] Abstract and §4 (Experimental Results): the headline performance claims (1000× task metrics, 2.19× FID) rest on the post-processing filter eliminating invalid sequences, yet no acceptance-rate statistics, before/after distribution comparisons, or ablation isolating the filter versus the backbone are supplied. Without these, it is impossible to rule out that reported gains arise from aggressive curation rather than improved generation.

    Authors: We agree that the current manuscript does not supply acceptance-rate statistics, before/after comparisons, or an explicit ablation of the filter versus the backbone alone. The reported metrics reflect the end-to-end Phantom system, where the filter is required to produce any usable traces; the backbone by itself yields sequences that violate PCIe rules and are therefore invalid for simulation. In the revision we will add the requested statistics, distribution comparisons, and ablation to demonstrate that the gains arise from the filter enabling valid generation rather than from curation of an already capable model. revision: yes

  2. Referee: [§3] §3 (Methodology): the description of the novel filter states only that it 'eliminates invalid TLP sequences' without specifying the exact rules enforced, the fraction of outputs retained, or any proof that retained traces preserve the backbone model's statistical properties for downstream simulation utility.

    Authors: Section 3 and the abstract note that the filter enforces PCIe constraints such as ordering and causality. We acknowledge that the current text does not enumerate the precise rules, report retention fractions, or include a statistical-preservation analysis. The revised manuscript will expand the filter description with the exact rules, the observed retention rates on the evaluated traces, and supporting measurements showing that key distributional properties (traffic volume, inter-packet timing) relevant to simulation are retained after filtering. revision: yes

Circularity Check

0 steps flagged

No significant circularity in derivation chain

full rationale

The paper presents Phantom as a generative backbone coupled to a post-processing filter that applies external PCIe protocol rules (ordering, causality) to remove invalid TLP sequences. Performance claims rest on empirical comparisons (FID, task-specific metrics) against backbone-only baselines on traces from a real NIC, with no equations, fitted parameters, or self-citations shown to define the reported gains by construction. The filter's constraints derive from the published PCIe specification rather than from quantities fitted or renamed within the paper itself, rendering the central claims independent of the listed circularity patterns.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 1 invented entities

Abstract-only review; no explicit free parameters, axioms, or invented entities are described beyond the introduction of the Phantom framework itself.

invented entities (1)
  • post-processing filter no independent evidence
    purpose: enforce PCIe-specific constraints and eliminate invalid TLP sequences
    Presented as the novel component that resolves hallucinations

pith-pipeline@v0.9.0 · 5810 in / 1132 out tokens · 38605 ms · 2026-05-23T16:59:16.191502+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

47 extracted references · 47 canonical work pages · 3 internal anchors

  1. [1]

    , " * write output.state after.block = add.period write newline

    ENTRY address archivePrefix author booktitle chapter edition editor eid eprint howpublished institution isbn journal key month note number organization pages publisher school series title type volume year label extra.label sort.label short.list INTEGERS output.state before.all mid.sentence after.sentence after.block FUNCTION init.state.consts #0 'before.a...

    work page

  2. [2]

    write newline

    " write newline "" before.all 'output.state := FUNCTION n.dashify 't := "" t empty not t #1 #1 substring "-" = t #1 #2 substring "--" = not "--" * t #2 global.max substring 't := t #1 #1 substring "-" = "-" * t #2 global.max substring 't := while if t #1 #1 substring * t #2 global.max substring 't := if while FUNCTION word.in bbl.in capitalize " " * FUNCT...

    work page

  3. [3]

    GPT-4 Technical Report

    Achiam, J.; Adler, S.; Agarwal, S.; Ahmad, L.; Akkaya, I.; Aleman, F. L.; Almeida, D.; Altenschmidt, J.; Altman, S.; Anadkat, S.; et al. 2023. GPT-4 technical report. arXiv preprint arXiv:2303.08774

    work page internal anchor Pith review Pith/arXiv arXiv 2023

  4. [4]

    Arafa, Y.; Badawy, A.-H.; ElWazir, A.; Barai, A.; Eker, A.; Chennupati, G.; Santhi, N.; and Eidenbenz, S. 2021. Hybrid, Scalable, Trace-Driven Performance Modeling of GPGPUs. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC '21), 53:1--53:15

    work page 2021

  5. [5]

    Bai, C.; Zhai, J.; Ma, Y.; Yu, B.; and Wong, M. D. F. 2024. Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning. In Proceedings of the AAAI Conference on Artificial Intelligence (AAAI '24), volume 38, 12--20

    work page 2024

  6. [6]

    Chen, R.; Peng, W.; Li, Y.; Liu, X.; and Wang, G. 2023. Orchid: An Online Learning Based Resource Partitioning Framework for Job Colocation with Multiple Objectives. IEEE Transactions on Computers (TC)

    work page 2023

  7. [7]

    Chen, Y.; Hu, Z.; Zhi, C.; Han, J.; Deng, S.; and Yin, J. 2024. ChatUniTest: A Framework for LLM-Based Test Generation. In Companion Proceedings of the 32nd ACM International Conference on the Foundations of Software Engineering (FSE 2024), 572--576

    work page 2024

  8. [8]

    Cornanguer, L.; Largou \"e t, C.; Roz \'e , L.; and Termier, A. 2022. TAG: Learning Timed Automata from Logs. In Proceedings of the AAAI Conference on Artificial Intelligence (AAAI '22), volume 36, 3949--3958

    work page 2022

  9. [9]

    Fan, Z.; Gao, X.; Mirchev, M.; Roychoudhury, A.; and Tan, S. H. 2023. Automated Repair of Programs from Large Language Models. In Proceedings of the 2023 IEEE/ACM 45th International Conference on Software Engineering (ICSE '23), 1469--1481

    work page 2023

  10. [10]

    Gu, Q. 2023. LLM-Based Code Generation Method for Golang Compiler Testing. In Proceedings of the 31st ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering (ESEC/FSE 2023), 2201--2203

    work page 2023

  11. [11]

    Guo, H.; Yang, J.; Liu, J.; Bai, J.; Wang, B.; Li, Z.; Zheng, T.; Zhang, B.; Peng, J.; and Tian, Q. 2024. Logformer: A Pre-train and Tuning Pipeline for Log Anomaly Detection. In Proceedings of the AAAI Conference on Artificial Intelligence (AAAI '24), volume 38, 135--143

    work page 2024

  12. [12]

    Han, M.; Zhang, H.; Chen, R.; and Chen, H. 2022. Microsecond-Scale Preemption for Concurrent GPU-Accelerated DNN Inferences. In Proceedings of the 16th USENIX Symposium on Operating Systems Design and Implementation (OSDI '22), 539--558

    work page 2022

  13. [13]

    Hester, J.; and Sorber, J. 2017. Flicker: Rapid Prototyping for the Batteryless Internet-of-Things. In Proceedings of the 15th ACM Conference on Embedded Network Sensor Systems (SenSys '17), 19:1--19:13

    work page 2017

  14. [14]

    Heusel, M.; Ramsauer, H.; Unterthiner, T.; Nessler, B.; and Hochreiter, S. 2017. GANs Trained by a Two Time-Scale Update Rule Converge to a Local Nash Equilibrium. In Advances in Neural Information Processing Systems (NeurIPS '17), volume 30

    work page 2017

  15. [15]

    Hong, Z.; Fan, X.; Jiang, T.; and Feng, J. 2020. End-to-End Unpaired Image Denoising with Conditional Adversarial Networks. In Proceedings of the AAAI Conference on Artificial Intelligence (AAAI '20), volume 34, 4140--4149

    work page 2020

  16. [16]

    MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications

    Howard, A. G.; Zhu, M.; Chen, B.; Kalenichenko, D.; Wang, W.; Weyand, T.; Andreetto, M.; and Adam, H. 2017. MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications. ArXiv preprint, abs/1704.04861

    work page internal anchor Pith review Pith/arXiv arXiv 2017

  17. [17]

    Hu, Z.; Yang, Z.; Liang, X.; Salakhutdinov, R.; and Xing, E. P. 2017. Toward Controlled Generation of Text. In Proceedings of the 34th International Conference on Machine Learning (ICML '17), volume 70 of Proceedings of Machine Learning Research, 1587--1596

    work page 2017

  18. [18]

    Ij, H. 2018. Statistics versus Machine Learning. Nature Methods, 15(4): 233

    work page 2018

  19. [19]

    N.; Schmitt, P.; Bronzino, F.; and Feamster, N

    Jiang, X.; Liu, S.; Gember-Jacobson, A.; Bhagoji, A. N.; Schmitt, P.; Bronzino, F.; and Feamster, N. 2024. Netdiffusion: Network Data Augmentation through Protocol-Constrained Traffic Generation. Proceedings of the ACM on Measurement and Analysis of Computing Systems (POMACS), 8(1): 1--32

    work page 2024

  20. [20]

    Kim, H.; Ryu, J.; and Lee, J. 2024. TCCL: Discovering Better Communication Paths for PCIe GPU Clusters. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '24), 999--1015

    work page 2024

  21. [21]

    Kuga, Y.; Nakamura, R.; Matsuya, T.; and Sekiya, Y. 2020. NetTLP: A Development Platform for PCIe Devices in Software Interacting with Hardware. In Proceedings of the 17th USENIX Symposium on Networked Systems Design and Implementation (NSDI '20), 141--155

    work page 2020

  22. [22]

    Li, B.; Qi, X.; Lukasiewicz, T.; and Torr, P. 2019. Controllable Text-to-Image Generation. In Advances in Neural Information Processing Systems (NeurIPS '19), volume 32

    work page 2019

  23. [23]

    Li, H.; Li, J.; and Kaufmann, A. 2022. SimBricks: End-to-End Network System Evaluation with Modular Simulation. In Proceedings of the ACM SIGCOMM 2022 Conference (SIGCOMM '22), 380--396

    work page 2022

  24. [24]

    A.; Shih, K

    Liu, G.; Reda, F. A.; Shih, K. J.; Wang, T.-C.; Tao, A.; and Catanzaro, B. 2018. Image Inpainting for Irregular Holes Using Partial Convolutions. In Proceedings of the European Conference on Computer Vision (ECCV '18), 85--100

    work page 2018

  25. [25]

    Liu, Y.; Tao, S.; Meng, W.; Yao, F.; Zhao, X.; and Yang, H. 2024. LogPrompt: Prompt Engineering Towards Zero-Shot and Interpretable Log Analysis. In Proceedings of the 2024 IEEE/ACM 46th International Conference on Software Engineering: Companion Proceedings (ICSE-Companion '24), 364--365

    work page 2024

  26. [26]

    F.; Audzevich, Y.; L\' o pez-Buedo, S.; and Moore, A

    Neugebauer, R.; Antichi, G.; Zazo, J. F.; Audzevich, Y.; L\' o pez-Buedo, S.; and Moore, A. W. 2018. Understanding PCIe Performance for End Host Networking. In Proceedings of the 2018 Conference of the ACM Special Interest Group on Data Communication (SIGCOMM '18), 327--341

    work page 2018

  27. [27]

    Nitin, V.; Asthana, S.; Ray, B.; and Krishna, R. 2022. Cargo: AI-Guided Dependency Analysis for Migrating Monolithic Applications to Microservices Architecture. In Proceedings of the 37th IEEE/ACM International Conference on Automated Software Engineering (ASE '22), 1--12

    work page 2022

  28. [28]

    Peng, B.; Zhang, H.; Yao, J.; Dong, Y.; Xu, Y.; and Guan, H. 2018. MDev-NVMe: A NVMe Storage Virtualization Solution with Mediated Pass-Through. In Proceedings of the 2018 USENIX Annual Technical Conference (USENIX ATC '18), 665--676

    work page 2018

  29. [29]

    M.; Kadekodi, S.; Ghodrati, S.; Moon, S.; and Maas, M

    Phothilimthana, P. M.; Kadekodi, S.; Ghodrati, S.; Moon, S.; and Maas, M. 2024. Thesios: Synthesizing Accurate Counterfactual I/O Traces from I/O Samples. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '24), 1016--1032

    work page 2024

  30. [30]

    Raghav, S.; Marongiu, A.; Pinto, C.; Atienza, D.; Ruggiero, M.; and Benini, L. 2012. Full System Simulation of Many-Core Heterogeneous SoCs Using GPU and QEMU Semihosting. In Proceedings of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units (GPGPU-5), 101--109

    work page 2012

  31. [31]

    D.; Shashua, A.; Leyton-Brown, K.; and Shoham, Y

    Ratner, N.; Levine, Y.; Belinkov, Y.; Ram, O.; Magar, I.; Abend, O.; Karpas, E. D.; Shashua, A.; Leyton-Brown, K.; and Shoham, Y. 2022. Parallel Context Windows for Large Language Models. In Proceedings of the Annual Meeting of the Association for Computational Linguistics (ACL '22)

    work page 2022

  32. [32]

    Rombach, R.; Blattmann, A.; Lorenz, D.; Esser, P.; and Ommer, B. 2022. High-Resolution Image Synthesis with Latent Diffusion Models. In Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR '22), 10684--10695

    work page 2022

  33. [33]

    B.; Patel, T.; and Tiwari, D

    Roy, R. B.; Patel, T.; and Tiwari, D. 2021. Satori: Efficient and Fair Resource Partitioning by Sacrificing Short-Term Benefits for Long-Term Gains. In Proceedings of the 48th Annual International Symposium on Computer Architecture (ISCA '21), 292--305

    work page 2021

  34. [34]

    N.; Krishnamurthy, A.; Culler, D.; Levy, H

    Schuh, H. N.; Krishnamurthy, A.; Culler, D.; Levy, H. M.; Rizzo, L.; Khan, S.; and Stephens, B. E. 2024. CC-NIC: a Cache-Coherent Interface to the NIC. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '24), 52--68

    work page 2024

  35. [35]

    Szegedy, C.; Vanhoucke, V.; Ioffe, S.; Shlens, J.; and Wojna, Z. 2016. Rethinking the Inception Architecture for Computer Vision. In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR '16), 2818--2826

    work page 2016

  36. [36]

    L.; and Stone, H

    Thiebaut, D.; Wolf, J. L.; and Stone, H. S. 1992. Synthetic Traces for Trace-Driven Simulation of Cache Memories. IEEE Transactions on Computers (TC), 41(4): 388--410

    work page 1992

  37. [37]

    Touvron, H.; Lavril, T.; Izacard, G.; Martinet, X.; Lachaux, M.-A.; Lacroix, T.; Rozi \`e re, B.; Goyal, N.; Hambro, E.; Azhar, F.; et al. 2023. Llama: Open and Efficient Foundation Language Models. arXiv preprint arXiv:2302.13971

    work page internal anchor Pith review Pith/arXiv arXiv 2023

  38. [38]

    R.; Baerwolf, R.; Knowles, N.; Hutchinson, B.; Nichols, N.; and Jasper, R

    Tuor, A. R.; Baerwolf, R.; Knowles, N.; Hutchinson, B.; Nichols, N.; and Jasper, R. 2018. Recurrent Neural Network Language Models for Open Vocabulary Event-Level Cyber Anomaly Detection. In Proceedings of the Workshops at the Thirty-Second AAAI Conference on Artificial Intelligence (AAAI '18)

    work page 2018

  39. [39]

    Z.; Dhakal, A.; Cao, L.; Sharma, P.; and Kuzmanovic, A

    Xiao, Y.; Tootaghaj, D. Z.; Dhakal, A.; Cao, L.; Sharma, P.; and Kuzmanovic, A. 2024. Conspirator: SmartNIC-Aided Control Plane for Distributed ML Workloads. In Proceedings of the 2024 USENIX Annual Technical Conference (USENIX ATC '24), 767--784

    work page 2024

  40. [40]

    B.; Lin, Y.; and Pan, D

    Ye, W.; Alawieh, M. B.; Lin, Y.; and Pan, D. Z. 2019. LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks. In Proceedings of the 56th Annual Design Automation Conference 2019 (DAC '19), 107:1--107:6

    work page 2019

  41. [41]

    Yin, Y.; Lin, Z.; Jin, M.; Fanti, G.; and Sekar, V. 2022. Practical GAN-based Synthetic IP Header Trace Generation using NetShare. In Proceedings of the ACM SIGCOMM 2022 Conference (SIGCOMM '22), 458--472

    work page 2022

  42. [42]

    K.; Jin, H.; Xu, C.; and Wu, J

    Yu, Z.; Eeckhout, L.; Goswami, N.; Li, T.; John, L. K.; Jin, H.; Xu, C.; and Wu, J. 2015. GPGPU-MiniBench: Accelerating GPGPU Micro-Architecture Simulation. IEEE Transactions on Computers (TC), 64(11): 3153--3166

    work page 2015

  43. [43]

    Yuan, Y.; Alian, M.; Wang, Y.; Wang, R.; Kurakin, I.; Tai, C.; and Kim, N. S. 2021. Don't Forget the I/O When Allocating Your LLC. In Proceedings of the 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA '21), 112--125

    work page 2021

  44. [44]

    Zhang, J.; Huang, H.; Zhu, L.; Ma, S.; Rong, D.; Hou, Y.; Sun, M.; Gu, C.; Cheng, P.; Shi, C.; and Wang, Z. 2023. SmartDS: Middle-Tier-centric SmartNIC Enabling Application-aware Message Split for Disaggregated Block Storage. In Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA '23), 42:1--42:13

    work page 2023

  45. [45]

    Zhao, H.; Cui, W.; Chen, Q.; Zhang, Y.; Lu, Y.; Li, C.; Leng, J.; and Guo, M. 2022. Tacker: Tensor-CUDA Core Kernel Fusion for Improving the GPU Utilization While Ensuring QoS. In Proceedings of the 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA '22), 800--813

    work page 2022

  46. [46]

    Zheng, S.; Yang, H.; Zhu, B.; Yu, B.; and Wong, M. 2023. LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing. In Advances in Neural Information Processing Systems (NeurIPS '23), 30243--30254

    work page 2023

  47. [47]

    Zheng, Y.; Pujar, S.; Lewis, B.; Buratti, L.; Epstein, E.; Yang, B.; Laredo, J.; Morari, A.; and Su, Z. 2021. D2a: A Dataset Built for AI-Based Vulnerability Detection Methods Using Differential Analysis. In Proceedings of the 2021 IEEE/ACM 43rd International Conference on Software Engineering: Software Engineering in Practice (ICSE-SEIP '21), 111--120

    work page 2021