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Bounds for Quantum Circuits using Logic-Based Analysis
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Bounds for Quantum Circuits using Logic-Based Analysis
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We explore ideas for scaling verification methods for quantum circuits using SMT (Satisfiability Modulo Theories) solvers. We propose two primary strategies: (1) decomposing proof obligations via compositional verification and (2) leveraging linear over-approximation techniques for gate effects. We present two examples and demonstrate the application of these ideas to proof Hamming weight preservation.
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