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Sensitivity-Adapted Closed-Loop Optimization for High-Fidelity Controlled-Z Gates in Superconducting Qubits

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arxiv 2412.17454 v1 pith:2ZDDL4OK submitted 2024-12-23 quant-ph

Sensitivity-Adapted Closed-Loop Optimization for High-Fidelity Controlled-Z Gates in Superconducting Qubits

classification quant-ph
keywords pulsesuperconductinggateshigh-fidelityoptimizationqubitsclosed-loopcontrolled-z
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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Achieving fast and high-fidelity qubit operations is crucial for unlocking the potential of quantum computers. In particular, reaching low gate errors in two-qubit gates has been a long-standing challenge in the field of superconducting qubits due to their typically long duration relative to coherence times. To realize fast gates, we utilize the hybridization between fixed-frequency superconducting qubits with a strongly interacting coupler mode that is tunable in frequency. To reduce population leakage during required adiabatic passages through avoided level crossings, we employ a sensitivity-adaptive closed-loop optimization method to design complex pulse shapes. We compare the performance of Gaussian-square, Fourier-series, and piecewise-constant-slope (PiCoS) pulse parametrizations and are able to reach 99.9 % controlled-Z gate fidelity using a 64 ns long Fourier-series pulse defined by only seven parameters. These high-fidelity values are achieved by analyzing the optimized pulse shapes to identify and systematically mitigate signal-line distortions in the experiment. To improve the convergence speed of the optimization we implement an adaptive cost function, which continuously maximizes the sensitivity. The demonstrated method can be used for tune-up and recalibration of superconducting quantum processors.

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Cited by 1 Pith paper

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  1. Transmon Phase Gates Controlled by Superconducting Soliton DAC

    quant-ph 2026-07 conditional novelty 6.5

    A soliton-based superconducting DAC performs 5.6 ns transmon S-gates with 0.05% excitation error and strong noise rejection, limited in multi-DAC chips by 1.6% non-local phase errors from EMI.