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arxiv: 2601.14387 · v2 · submitted 2026-01-20 · ❄️ cond-mat.stat-mech

Optimal control of bit erasure in stochastic random access memory

Songela W. Chen , David T. Limmer This is my paper

Pith reviewed 2026-05-16 11:58 UTC · model grok-4.3

classification ❄️ cond-mat.stat-mech
keywords bit erasurerandom access memoryCMOSthermodynamic coststochastic dynamicsoptimal controlenergy dissipationquasistatic limit
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The pith

Dynamic random access memory dissipates the least energy erasing bits when run in the slow quasistatic limit, while static memory does better at finite times.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper models bit erasure in complementary metal oxide semiconductor versions of dynamic and static random access memory. It finds that dynamic memory erases bits with minimal energy dissipation and fewest errors when the operation is slow enough to stay near equilibrium. Static memory, by contrast, expends less total energy when erased faster because it must constantly supply power to hold its state. The authors introduce an optimization method based on mean-field theory and automatic differentiation to identify effective voltage protocols for these memory types.

Core claim

In a stochastic model of dynamic random access memory, the energy cost of bit erasure reaches its minimum in the quasistatic limit, where the process proceeds slowly and bit errors are also minimized. In the corresponding model of static random access memory, finite-time operation yields lower energy costs because the energy required to maintain the bit state grows with the duration of the protocol.

What carries the argument

Mean-field stochastic dynamics of CMOS circuit models optimized via automatic differentiation to find minimal-energy voltage protocols.

If this is right

  • DRAM should be operated slowly for thermodynamically efficient bit erasure.
  • SRAM benefits from shorter erasure times to reduce the cumulative cost of state maintenance.
  • The optimization framework produces protocols consistent with established electrical engineering practices.
  • Similar methods can identify advantageous operating regimes for other memory technologies.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • This distinction implies that memory type should influence the speed chosen for erasure operations in energy-constrained devices.
  • Extending the model to include more detailed device physics could reveal additional trade-offs.
  • These results may inform protocols for large-scale data centers where memory energy use is significant.

Load-bearing premise

The chosen CMOS circuit models and their mean-field treatment accurately reflect the stochastic dynamics and energy use of real DRAM and SRAM devices.

What would settle it

Direct measurements of energy dissipation and error rates in physical DRAM chips during bit erasure at different speeds, compared against the quasistatic prediction.

Figures

Figures reproduced from arXiv: 2601.14387 by David T. Limmer, Songela W. Chen.

Figure 1
Figure 1. Figure 1: FIG. 1. Schematic of bit erasure and related timescales. (a) Controlled bit erasure, driven by time-dependent [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. Dynamic random access memory (DRAM) phe [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Heat-accuracy tradeoffs observed in DRAM, aver [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Static random access memory (SRAM) phenomenology. (a) One of two coupled [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. Heat-accuracy tradeoffs observed in SRAM, aver [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. Loss function starting from random seed. [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. Heat-accuracy tradeoffs observed in SRAM, averaged [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. Dissipated heat for DRAM under a linearly varying [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9. Dissipated heat for SRAM, linearly varying bitline [PITH_FULL_IMAGE:figures/full_fig_p010_9.png] view at source ↗
read the original abstract

Energy costs of information processing are growing exponentially. Bit erasure is a key problem in this energy-information nexus, and a number of seminal relationships have been deduced regarding the relationship between thermodynamic costs and memory storage. To continue making progress in the modern era, however, requires confronting thermodynamic costs in realistic physical systems which operate away from equilibrium. Here, we explore the thermodynamic costs of bit erasure in a complementary metal oxide semiconductor model of two types of random access memory. We find dynamic random access memory dissipates the least amount of energy when operated in the quasistatic limit, where errors are also minimized. By contrast, static random access memory is most efficiently operated in finite time due to the energy required to maintain the state of the bit. We demonstrate a numerically robust optimization scheme using mean field theory and automatic differentiation, finding optimal protocols compatible with electrical engineering insights. These results provide a framework for operating realistic circuits in thermodynamically advantageous ways.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper examines thermodynamic costs of bit erasure in CMOS-based models of DRAM and SRAM. Using mean-field theory combined with automatic differentiation, it optimizes voltage protocols and reports that DRAM achieves minimal dissipation and error rates in the quasistatic limit, whereas SRAM is most efficient at finite times because of the energy cost of maintaining the bit state. The work presents a numerically robust optimization framework claimed to be compatible with electrical-engineering practice.

Significance. If the mean-field results survive stochastic validation, the distinction between DRAM and SRAM operating regimes supplies a concrete, device-relevant example of how stochastic thermodynamics can guide low-energy memory design. The automatic-differentiation approach to protocol optimization is a clear methodological strength that could be reused in other circuit models.

major comments (2)
  1. [Methods / Optimization procedure] The headline claim that DRAM is optimally quasistatic while SRAM is optimally finite-time rests entirely on trajectories obtained inside the mean-field approximation to the CMOS circuit equations. No comparison to direct stochastic integration (Langevin or master-equation) of the same protocols is reported, leaving open the possibility that fluctuations shift the location or depth of the dissipation minimum by more than a few kT.
  2. [Results] The abstract and results sections assert that the reported protocols are “compatible with electrical engineering insights,” yet no quantitative error analysis, sensitivity study with respect to the mean-field closure, or comparison against measured device dissipation data is provided to support the quantitative efficiency numbers.
minor comments (1)
  1. [Model section] Notation for the voltage protocols and the precise definition of the mean-field order parameter should be stated explicitly in the main text rather than deferred to supplementary material.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the constructive comments and positive assessment of the work's significance. We address the major comments point by point below, committing to revisions that strengthen the manuscript while remaining faithful to the mean-field framework used.

read point-by-point responses

  1. Referee: [Methods / Optimization procedure] The headline claim that DRAM is optimally quasistatic while SRAM is optimally finite-time rests entirely on trajectories obtained inside the mean-field approximation to the CMOS circuit equations. No comparison to direct stochastic integration (Langevin or master-equation) of the same protocols is reported, leaving open the possibility that fluctuations shift the location or depth of the dissipation minimum by more than a few kT.

    Authors: We agree that stochastic validation would further bolster the results. The mean-field closure is appropriate here because CMOS devices involve large carrier numbers (typically 10^4–10^6 electrons per node), rendering relative fluctuations small (∼1/√N ≪ 1). In the revised manuscript we will add a dedicated subsection performing Langevin stochastic integration of the optimized protocols, showing that the dissipation minima locations and depths shift by less than 1 kT, thereby confirming that the quasistatic versus finite-time distinction survives fluctuations. revision: yes

  2. Referee: [Results] The abstract and results sections assert that the reported protocols are “compatible with electrical engineering insights,” yet no quantitative error analysis, sensitivity study with respect to the mean-field closure, or comparison against measured device dissipation data is provided to support the quantitative efficiency numbers.

    Authors: We will revise the abstract and results to clarify that compatibility refers to qualitative agreement with established practices (slow ramps in DRAM to reduce leakage, finite-time operation in SRAM to limit static power). A new sensitivity subsection will vary key parameters (threshold voltages, capacitances, temperature) and report error bars on the efficiency numbers. Direct comparison to experimental dissipation data from fabricated chips lies outside the scope of this theoretical study and would require proprietary process parameters; we will explicitly note this limitation. revision: partial

standing simulated objections not resolved
  • Direct quantitative comparison to measured dissipation values from fabricated DRAM/SRAM devices, which would require access to proprietary fabrication data and experimental collaboration.

Circularity Check

0 steps flagged

No significant circularity; optimization follows from physical model equations

full rationale

The paper derives optimal protocols for bit erasure by applying mean-field theory to CMOS circuit equations and using automatic differentiation for numerical optimization. The reported distinction (DRAM quasistatic optimum, SRAM finite-time optimum) emerges directly from the deterministic dynamics of the mean-field model under different voltage protocols, without any parameter fitting to the target efficiency metrics or self-referential definitions. No steps reduce by construction to inputs, and the derivation remains self-contained against the stated model assumptions.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Central claims rest on the validity of the chosen CMOS equivalent-circuit models, the mean-field closure for stochastic dynamics, and the assumption that the automatic-differentiation optimizer finds globally relevant minima.

axioms (1)
  • domain assumption Mean-field approximation suffices to capture the essential stochastic thermodynamics of the memory cells
    Invoked to enable tractable optimization of the erasure protocols

pith-pipeline@v0.9.0 · 5456 in / 1142 out tokens · 20112 ms · 2026-05-16T11:58:44.170070+00:00 · methodology

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