pith. sign in

arxiv: 2606.30805 · v1 · pith:MTIZIKVQnew · submitted 2026-06-29 · 🪐 quant-ph · cs.AR· cs.ET

CryoZip: An Efficient Cryogenic Compressor for Quantum Error Correction Syndromes

Guanchen Tao , Alexander Knapen , Jacob Mack , Gokul Subramanian Ravi , Qirui Zhang , Mehdi Saligane , Dennis Sylvester This is my paper

Pith reviewed 2026-07-01 01:33 UTC · model grok-4.3

classification 🪐 quant-ph cs.ARcs.ET
keywords cryogenic compressionquantum error correctionsyndrome transmissionfault tolerant quantum computingenergy efficient hardware4K to room temperature interfacesliding window compression
0
0 comments X

The pith

CryoZip compresses quantum error correction syndromes by up to 48 times at 4 Kelvin using a sliding-window architecture.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces CryoZip, a compression framework that works at cryogenic temperatures alongside a lightweight QEC predecoder to shrink the volume of syndrome data sent from the 4 K stage to room temperature. It targets the bandwidth and power limits that constrain scaling of fault-tolerant quantum computers by applying a sliding-window compressor sized to meet decoding latency rules. The approach delivers large reductions in transmitted data and energy when syndromes are sparse. A reader would care because these interface constraints are a primary barrier to building bigger quantum processors without enormous added infrastructure.

Core claim

CryoZip is a cross-stack cryogenic compression framework that cooperates with a lightweight QEC predecoder to reduce 4 K to RT syndrome transmission under realistic circuit-level noise. It targets sparse syndrome vectors with a sliding window compression architecture sized under strict decoding latency constraints to maximize energy efficiency. Implemented in 22 nm FDSOI at 4 K, it achieves up to 48x compression (1.8x higher than prior compressors) across QEC codes, 4-26x energy savings, over 14,238x bandwidth reduction when paired with the predecoder, and up to 42x energy savings including interface overheads.

What carries the argument

The sliding-window compression architecture sized under strict decoding latency constraints to operate on sparse syndrome vectors while maximizing energy efficiency.

If this is right

  • Up to 48x compression across various QEC codes, 1.8x better than existing compressors.
  • 4 to 26x energy savings in the 22 nm FDSOI implementation characterized at 4 K.
  • Over 14,238x bandwidth reduction when the compressor is paired with the QEC predecoder.
  • Energy savings increase to 42x once realistic QEC interface overheads are included.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The method could support larger qubit counts by keeping the cold-to-warm data link from becoming the dominant power consumer.
  • Design choices here may encourage co-optimization of predecoders and compressors in other quantum interface problems.
  • If the sparsity assumption weakens at higher error rates, the architecture would need adjustable window sizes to stay effective.

Load-bearing premise

Syndrome vectors remain sufficiently sparse and the predecoder sufficiently lightweight that the sliding-window compressor fits inside the decoding latency budget under realistic circuit-level noise.

What would settle it

An end-to-end measurement of compression ratio, energy use, and total latency for CryoZip running inside a full QEC cycle with circuit-level noise to determine whether it exceeds the allowed decoding window or delivers less than the claimed compression.

Figures

Figures reproduced from arXiv: 2606.30805 by Alexander Knapen, Dennis Sylvester, Gokul Subramanian Ravi, Guanchen Tao, Jacob Mack, Mehdi Saligane, Qirui Zhang.

Figure 1
Figure 1. Figure 1: Landscape of classical hardware solutions for QEC. [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Lattice (left) and syndrome measurement circuit [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 5
Figure 5. Figure 5: SD algorithm operation: (a) normal processing; (b) saturation when 𝑚𝑎𝑥_𝑑𝑖𝑠𝑡𝑎𝑛𝑐𝑒 is reached; (c) distribution of emitted distances. by analyzing the statistical frequency of distance values produced by the SD stage, from which a Huffman tree is generated to as￾sign optimal binary codes to each distance symbol. This codebook remains static during the compression. Leveraging the observation that syndromes rem… view at source ↗
Figure 4
Figure 4. Figure 4: CryoZip algorithm consists of SD and HEnc. Huff￾man codebook used for HEnc is generated offline. load from cross-temperature cabling further worsens this bottle￾neck [21, 32]. These limits motivate reducing 4 K-to-RT syndrome bandwidth to enable scalable quantum computing systems. 3 CryoZip Compression Algorithm We begin by introducing CryoZip, a lightweight compression al￾gorithm designed to encode the sy… view at source ↗
Figure 7
Figure 7. Figure 7: Sliding window compression hardware is able to [PITH_FULL_IMAGE:figures/full_fig_p004_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Pipelined architecture of CryoZip (above) and sched [PITH_FULL_IMAGE:figures/full_fig_p004_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: (a) Dependence of CryoZip compression ratio on [PITH_FULL_IMAGE:figures/full_fig_p005_9.png] view at source ↗
Figure 11
Figure 11. Figure 11: (a) Bandwidth savings on the surface code for AFS, CryoZip, and CryoZip with the predecoder; (b) Total energy [PITH_FULL_IMAGE:figures/full_fig_p006_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Compression ratio comparison of AFS and CryoZip [PITH_FULL_IMAGE:figures/full_fig_p006_12.png] view at source ↗
read the original abstract

Scaling fault tolerant quantum computing is increasingly constrained by the limited bandwidth and power budget across the 4 K to room temperature (RT) interface. We present CryoZip, a cross stack cryogenic compression framework that cooperates with a lightweight cryogenic quantum error correction (QEC) predecoder to reduce 4 K to RT syndrome transmission under realistic, circuit level noise. CryoZip targets sparse syndrome vectors with a sliding window compression architecture sized under strict decoding latency constraints to maximize energy efficiency. We implement and evaluate the design in 22 nm FDSOI characterized at 4 K, using vector based power, performance, and area analysis to obtain realistic hardware data. CryoZip achieves up to 48x compression, 1.8x higher than state of the art compressors, across various QEC codes while delivering 4 to 26x energy savings. When paired with a QEC predecoder, it yields over 14,238x bandwidth reduction, while energy savings rise to 42x when accounting for realistic QEC interface overheads.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript presents CryoZip, a cross-stack cryogenic compression framework for quantum error correction (QEC) syndromes that cooperates with a lightweight predecoder. It targets sparse syndrome vectors using a sliding-window architecture sized under decoding latency constraints, implemented and evaluated in 22 nm FDSOI at 4 K via vector-based power-performance-area analysis. The central claims are up to 48x compression (1.8x higher than state-of-the-art), 4–26x energy savings, and, when paired with the predecoder, over 14,238x bandwidth reduction and 42x energy savings under realistic circuit-level noise.

Significance. If the latency-budget and noise-model claims are substantiated, the work would be significant for alleviating the bandwidth and power constraints at the 4 K–room-temperature interface, a key scaling bottleneck for fault-tolerant quantum computing. The hardware characterization at cryogenic temperatures and the reported cooperation with a QEC predecoder are strengths that could enable practical deployment if the supporting metrics are provided.

major comments (2)
  1. [Abstract] Abstract: The headline claims (48x compression, 14,238x bandwidth reduction, 42x energy savings) rest on the assertion that the sliding-window compressor operates inside the QEC decoding latency budget under circuit-level noise with a lightweight predecoder. No quantitative values are supplied for (a) predecoder added latency or area, (b) the exact noise model or error rates determining syndrome sparsity, or (c) measured end-to-end latency compared with the QEC cycle time. This information is load-bearing for the central performance claims.
  2. [Abstract] Abstract (and evaluation section if present): The reported compression ratios and energy savings are stated to result from the predecoder cooperation, yet the abstract supplies no data tables, error bars, or verification steps for the PPA measurements or sparsity evaluation. Without these, it is impossible to assess whether the figures are robust or subject to post-hoc selection.
minor comments (1)
  1. [Abstract] Abstract: 'vector based' should be hyphenated as 'vector-based'.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their careful review and constructive feedback. We address each major comment below and have revised the manuscript to improve clarity and self-containment of the abstract while preserving its conciseness.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The headline claims (48x compression, 14,238x bandwidth reduction, 42x energy savings) rest on the assertion that the sliding-window compressor operates inside the QEC decoding latency budget under circuit-level noise with a lightweight predecoder. No quantitative values are supplied for (a) predecoder added latency or area, (b) the exact noise model or error rates determining syndrome sparsity, or (c) measured end-to-end latency compared with the QEC cycle time. This information is load-bearing for the central performance claims.

    Authors: The manuscript body supplies the requested quantitative values: predecoder latency and area overheads are quantified with cycle counts and area estimates in the hardware design section; the circuit-level noise model and corresponding error rates (which set syndrome sparsity) are specified in the noise model section; and end-to-end latency is compared against the QEC cycle time in the evaluation, confirming operation within budget. To address the abstract's brevity, we will revise it to include the key numerical values for these parameters along with explicit references to the supporting sections. revision: yes

  2. Referee: [Abstract] Abstract (and evaluation section if present): The reported compression ratios and energy savings are stated to result from the predecoder cooperation, yet the abstract supplies no data tables, error bars, or verification steps for the PPA measurements or sparsity evaluation. Without these, it is impossible to assess whether the figures are robust or subject to post-hoc selection.

    Authors: Abstracts are length-constrained and therefore omit data tables and error bars; these are provided in the evaluation section, which includes tables of compression and energy results across codes, error bars from repeated simulation runs, and explicit verification methodology for the 4 K PPA analysis and sparsity under the noise model. We will revise the abstract to state that results are obtained from verified multi-run simulations with full details in the main text, thereby clarifying robustness without altering the evaluation section. revision: yes

Circularity Check

0 steps flagged

No circularity; performance metrics derived from hardware implementation and empirical evaluation

full rationale

The paper reports compression ratios, bandwidth reductions, and energy savings obtained via direct implementation and characterization of the CryoZip design in 22 nm FDSOI at 4 K, using vector-based PPA analysis on measured hardware data. No equations, fitted parameters, or self-citations are invoked to derive these quantities by construction from the inputs; the central claims rest on external empirical results rather than self-referential definitions or renamed fits. The sliding-window architecture and predecoder cooperation are presented as design choices sized to latency constraints, but the reported numbers are not shown to reduce to those choices tautologically.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Only the abstract is available; no explicit free parameters, axioms, or invented entities are stated.

pith-pipeline@v0.9.1-grok · 5739 in / 1153 out tokens · 57545 ms · 2026-07-01T01:33:58.469222+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

38 extracted references · 9 canonical work pages · 1 internal anchor

  1. [1]

    Joseph Bardin, Evan Jeffrey, Erik Lucero, Trent Huang, Sayan Das, Daniel Sank, Ofer Naaman, Anthony Megrant, Rami Barends, Ted White, Marissa Giustina, Kevin Satzinger, Kunal Arya, Pedram Roushan, Benjamin Chiaro, Julian Kelly, Zijun Chen, Brian Burkett, Yu Chen, and John Martinis. 2019. Design and Char- acterization of a 28-nm Bulk-CMOS Cryogenic Quantum...

    work page doi:10.1109/jssc.2019.2937234 2019

  2. [2]

    Joseph Bardin, Evan Jeffrey, Erik Lucero, Trent Huang, Ofer Naaman, Rami Barends, Ted White, Marissa Giustina, Daniel Sank, Pedram Roushan, Kunal Arya, Benjamin Chiaro, Julian Kelly, Jimmy Chen, Brian Burkett, Yu Chen, Andrew Dunsworth, Austin Fowler, Brooks Foxen, and John Martinis. 2019. 29.1 A 28nm Bulk-CMOS 4-to-8GHz <2mW Cryogenic Pulse Modulator for...

    work page doi:10.1109/isscc.2019.8662480 2019

  3. [3]

    Michael E Beverland, Prakash Murali, Matthias Troyer, Krysta M Svore, Torsten Hoefler, Vadym Kliuchnikov, Guang Hao Low, Mathias Soeken, Aarthi Sundaram, and Alexander Vaschillo. 2022. Assessing requirements to scale to practical quantum advantage.arXiv preprint arXiv:2211.07629(2022)

    work page internal anchor Pith review Pith/arXiv arXiv 2022

  4. [4]

    Hector Bombin and Miguel Angel Martin-Delgado. 2006. Topological quantum distillation.Physical review letters97, 18 (2006), 180501

    2006

  5. [5]

    Sergey Bravyi, Andrew W Cross, Jay M Gambetta, Dmitri Maslov, Patrick Rall, and Theodore J Yoder. 2024. High-threshold and low-overhead fault-tolerant quantum memory.Nature627, 8005 (2024), 778–782

    2024

  6. [6]

    Baks, and Daniel Friedman

    Sudipto Chakraborty, David Frank, Kevin Tien, Pat Rosno, Mark Yeck, Joseph Glick, Raphael Robertazzi, Ray Richetta, John Bulzacchelli, Devin Underwood, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv Joshi, Shawn Chambers, Scott Lekuch, Ken Inoue, Dorothy Wisnieff, C. Baks, and Daniel Friedman. 2022. A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit...

    work page doi:10.1109/jssc.2022.3201775 2022

  7. [7]

    Junhyuk Choi, Ilkwon Byun, Juwon Hong, Dongmoon Min, Junpyo Kim, Jungmin Cho, Hyeonseong Jeong, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim. 2024. SuperCore: An Ultra-Fast Superconducting Processor for Cryogenic Applications. In2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 1532–1547

    2024

  8. [8]

    Marco Cusmai, Noam Familia, Elad Kuperberg, Mohammad Nashash, Dovid Gottesman, Daljeet Kumar, Zvi Marcus, Yeshayahu Horwitz, Sagi Zalcman, Ji- hwan Kim, et al. 2024. 7.2 A 224Gb/s sub pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET. In2024 IEEE International Solid-State Circuits Con- ference (ISSCC), Vol. 67. IEEE, 126–128

    2024

  9. [9]

    Poulami Das, Christopher A Pattison, Srilatha Manne, Douglas M Carmean, Krysta M Svore, Moinuddin Qureshi, and Nicolas Delfosse. 2022. Afs: Accu- rate, fast, and scalable error-decoding for fault-tolerant quantum computers. In 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, 259–273

    2022

  10. [10]

    Eric Dennis, Alexei Kitaev, Andrew Landahl, and John Preskill. 2002. Topological quantum memory.J. Math. Phys.43, 9 (2002), 4452–4505

    2002

  11. [11]

    Jeroen Dijk, Bishnu Patra, Sushil Subramanian, Xiao Xue, Nodar Samkharadze, Andrea Corna, Charles Jeon, Farhana Sheikh, Esdras Juarez-Hernandez, Brando Esparza, Huzaifa Rampurawala, Brent Carlton, Surej Ravikumar, Carlos Nieva, Sungwon Kim, Hyung-Jin Lee, Amir Sammak, Giordano Scappucci, Menno Veldhorst, and Fabio Sebastiano. 2020. A Scalable Cryo-CMOS Co...

    work page doi:10.1109/jssc 2020

  12. [12]

    Niels Fakkel, Mohsen Mortazavi, Ramon WJ Overwater, Fabio Sebastiano, and Masoud Babaie. 2024. A cryo-CMOS DAC-based 40-Gb/s PAM4 wireline trans- mitter for quantum computing.IEEE Journal of Solid-State Circuits59, 5 (2024), 1433–1446

    2024

  13. [13]

    Austin G Fowler, Matteo Mariantoni, John M Martinis, and Andrew N Cleland

  14. [14]

    Surface codes: Towards practical large-scale quantum computation.Physi- cal Review A—Atomic, Molecular, and Optical Physics86, 3 (2012), 032324

    2012

  15. [15]

    Baks, John Timmerwilke, and Daniel Friedman

    David Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Mark Yeck, Joseph Glick, Raphael Robertazzi, Ray Richetta, John Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv Joshi, Scott Lekuch, Ken Inoue, Devin Un- derwood, Dorothy Wisnieff, C. Baks, John Timmerwilke, and Daniel Friedman

  16. [16]

    In2023 IEEE Custom Integrated Circuits Conference (CICC)

    Low power cryogenic RF ASICs for quantum computing. In2023 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 1–8. doi:10.1109/CICC57935. 2023.10121266

    work page doi:10.1109/cicc57935 2023

  17. [17]

    Craig Gidney, Michael Newman, Austin Fowler, and Michael Broughton. 2021. A fault-tolerant honeycomb memory.Quantum5 (2021), 605

    2021

  18. [18]

    Adam Holmes, Mohammad Reza Jokar, Ghasem Pasandi, Yongshan Ding, Mas- soud Pedram, and Frederic T Chong. 2020. NISQ+: Boosting quantum computing power by approximating quantum error correction. In2020 ACM/IEEE 47th annual international symposium on computer architecture (ISCA). IEEE, 556–569

    2020

  19. [19]

    Andrea Husseiniova, Kauser Johar, Kenton Barnes, Aniket Datta, Canberk Topal, and Alex Zeffertt. 2025. QEC Interface for real-time quantum error correction. APS March Meeting. https://www.youtube.com/watch?v=raVomqQttfU

    2025

  20. [20]

    Toshiki Iwai, Kenichi Kawaguchi, Tetsuya Miyatake, Tetsuro Ishiguro, Shoichi Miyahara, Yoshiyasu Doi, Salahuddin Nur, Ryoichi Ishihara, and Shintaro Sato

  21. [21]

    In2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)

    Cryogenic Integration for Quantum Computer Using Diamond Color Center Spin Qubits. In2023 IEEE 73rd Electronic Components and Technology Conference (ECTC). IEEE, 967–972

  22. [22]

    Kiseo Kang, Donggyu Minn, Jaeho Lee, Ho-Jin Song, Moonjoo Lee, and Jae-Yoon Sim. 2023. 34.4 A Cryogenic Controller IC for Superconducting Qubits with DRAG Pulse Generation by Direct Synthesis without Using Memory. In2023 IEEE International Solid-State Circuits Conference (ISSCC). 33–35

    2023

  23. [23]

    Alexander Knapen, Guanchen Tao, Jacob Mack, Thomas Bruno, Mehdi Sali- gane, Dennis Sylvester, Qirui Zhang, and Gokul Subramanian Ravi. 2026. Pin- ball: A Cryogenic Predecoder for Quantum Error Correction Decoding Under Circuit-Level Noise. InProceedings of the IEEE International Symposium on High- Performance Computer Architecture (HPCA). To appear

    2026

  24. [24]

    Sebastian Krinner, Simon Storz, Philipp Kurpiers, Paul Magnard, Johannes Hein- soo, Raphael Keller, Janis Luetolf, Christopher Eichler, and Andreas Wallraff

  25. [25]

    Engineering cryogenic setups for 100-qubit scale superconducting circuit systems.EPJ Quantum Technology6, 1 (2019), 2

    2019

  26. [26]

    Jongseok Park, Sushil Subramanian, Lester Lampert, Todor Mladenov, Ilya Klotchkov, Dileep Kurian, Esdras Juarez-Hernandez, Brando Esparza, Sirisha Kale, Asma T., Shavindra Premaratne, Thomas Watson, Satoshi Suzuki, Mustafi- jur Rahman, Jaykant Timbadiya, Saksham Soni, and Stefano Pellerano. 2021. A Fully Integrated Cryo-CMOS SoC for State Manipulation, Re...

    work page doi:10.1109/jssc.2021.3115988 2021

  27. [27]

    Gokul Subramanian Ravi, Jonathan M Baker, Arash Fayyazi, Sophia Fuhui Lin, Ali Javadi-Abhari, Massoud Pedram, and Frederic T Chong. 2023. Better than worst-case decoding for quantum error correction. InProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2. 88–102

    2023

  28. [28]

    Quentin Schmidt, Baptiste Jadot, Brian Martinez, Antoine Faurie, Tristan Meu- nier, Jean-Baptiste Casanova, Xavier Jehl, Yvain Thonnart, and Franck Badets

  29. [29]

    In2025 IEEE International Solid-State Circuits Conference (ISSCC), Vol

    13.5 An 18.5 𝜇W/qubit Cryo-CMOS Charge-Readout IC Demonstrating QAM Multiplexing for Spin Qubits. In2025 IEEE International Solid-State Circuits Conference (ISSCC), Vol. 68. IEEE, 244–246

  30. [30]

    Luka Skoric, Dan E Browne, Kenton M Barnes, Neil I Gillespie, and Earl T Camp- bell. 2023. Parallel window decoding enables scalable fault tolerant quantum computation.Nature Communications14, 1 (2023), 7040

    2023

  31. [31]

    Barbara M Terhal. 2015. Quantum error correction for quantum memories. Reviews of Modern Physics87, 2 (2015), 307–346

    2015

  32. [32]

    Yosuke Ueno, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, and Yutaka Tabuchi. 2021. QECOOL: On-line quantum error correction with a supercon- ducting decoder for surface code. In2021 58th ACM/IEEE Design Automation Conference (DAC). IEEE, 451–456

    2021

  33. [33]

    Yosuke Ueno, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, and Yutaka Tabuchi. 2022. Qulatis: A quantum error correction methodology toward lattice surgery. In2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, 274–287

    2022

  34. [34]

    Baks, Raphael Robertazzi, Matthew Beck, Rajiv Joshi, Dorothy Wisnieff, Scott Lekuch, B

    Devin Underwood, Joseph Glick, Ken Inoue, David Frank, John Timmerwilke, Emily Pritchett, Sudipto Chakraborty, Kevin Tien, Mark Yeck, John Bulzacchelli, C. Baks, Raphael Robertazzi, Matthew Beck, Rajiv Joshi, Dorothy Wisnieff, Scott Lekuch, B. Gaucher, Daniel Friedman, Pat Rosno, and Jeff Ruedinger. 2024. Using Cryogenic CMOS Control Electronics to Enable...

    work page doi:10.1103/prxquantum.5.010326 2024

  35. [35]

    Jeroen PG van Dijk, Edoardo Charbon, and Fabio Sebastiano. 2019. The electronic interface for quantum processors.Microprocessors and Microsystems66 (2019), 90–101

    2019

  36. [36]

    Joshua Viszlai, Jason D Chadwick, Sarang Joshi, Gokul Subramanian Ravi, Yanjing Li, and Frederic T Chong. 2025. SWIPER: Minimizing Fault-Tolerant Quantum Program Latency via Speculative Window Decoding. InProceedings of the 52nd Annual International Symposium on Computer Architecture. 1386–1401

    2025

  37. [37]

    Jinchen Wang, Isaac Harris, Mohamed Ibrahim, Dirk Englund, and Ruonan Han. 2025. A wireless terahertz cryogenic interconnect that minimizes heat-to- information transfer.Nature Electronics(2025), 1–11

    2025

  38. [38]

    Juhwan Yoo, Zijun Chen, Frank Arute, Shirin Montazeri, Marco Szalay, Catherine Erickson, Evan Jeffrey, Reza Fatemi, Marissa Giustina, Markus Ansmann, Erik Lucero, Julian Kelly, and Joseph Bardin. 2023. 34.2 A 28-nm Bulk-CMOS IC for Full Control of a Superconducting Quantum Processor Unit-Cell. In2023 IEEE International Solid-State Circuits Conference (ISS...

    work page arXiv 2023