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REVIEW 3 major objections 6 minor 53 references

Origins of microwave losses in superconducting circuits made with silicon-on-insulator substrates

T0 review · 3 major / 6 minor · reviewed 2026-08-03 · deepseek-v4-flash

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Pith's one-line read High-resistivity SOI substrates are the worst of three SOI variants for cryogenic superconducting resonators, because a parasitic conductive sheet forms at the buried-oxide interface and dominates microwave loss.

desk verdict Solid empirical ranking of SOI substrates at mK; the PSC mechanism is plausible but rests on unmeasured oxide charge, so it deserves review but with a request for direct Qox constraints. read the letter →

arxiv 2607.29154 v1 pith:Z7OVL4DA submitted 2026-07-31 cond-mat.mes-hall quant-ph

Simon Messelot , Nicolas Aparicio , Kazi Rafsanjani Amin , Eric Eyraud , Bruno Fain , Mikaël Cassé , Guillaume Jourdan , Fabrice Nemouchi
show 6 more authors
Sébastien Hentz Frédéric Gustavo François Lefloch Nicolas Roch Jérémie J. Viennot Julien Renard
This is my paper
classification cond-mat.mes-hallquant-ph
keywords silicon-on-insulatorsuperconductingresonatorsmicrowavelosstwo-levelsystemsparasiticsurfaceconductiontrap-richSOITiNcryogenictemperatures
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that the standard assumption—use high-resistivity silicon to minimise microwave loss—fails for silicon-on-insulator (SOI) substrates at millikelvin temperatures. At cryogenic temperatures, a parasitic sheet conduction layer at the buried-oxide/silicon-handle interface makes high-resistivity SOI the worst performer (internal quality factors below 10^3), while standard-resistivity SOI is limited by residual doping. Adding a polycrystalline trap-rich layer under the buried oxide suppresses the parasitic sheet, yielding internal quality factors above 2×10^4 at the single-photon limit, limited only by dielectric losses in the silicon oxide. If correct, trap-rich SOI becomes a promising platform for superconducting electromechanical and microwave-to-optics devices, allowing the oxide to be kept under static parts.

What carries the argument

The central object is the parasitic surface conduction (PSC) layer: a thin, highly conductive sheet formed at the buried-oxide/silicon-handle interface by positive charge in the BOX that attracts mobile carriers. Its presence and magnitude are modeled with a 1D Poisson-Schrödinger solver, which yields a threshold oxide charge density (~10^10 cm^-2 for HR SOI and ~10^11 cm^-2 for Std SOI) below which the PSC disappears at 20 K. The paper uses this threshold to explain why HR SOI, despite its high bulk resistivity, suffers large low-temperature losses, and why intentionally introduced traps in trap-rich SOI suppress the PSC.

What would settle it

Measure the oxide charge density Qox on the same HR SOI and Std SOI wafers (e.g., by capacitance-voltage or Hall profiling) and compare with the simulation threshold; if Qox is below 10^10 cm^-2 on HR SOI, the PSC explanation fails. Also compare TiN critical temperature wafer-by-wafer to rule out film variation.

Watch

Extended reading notes

Core claim

The paper's central discovery is a counterintuitive substrate ranking and its mechanistic explanation. High-resistivity SOI substrates present the largest microwave losses of the three SOI variants studied, due to a parasitic surface conduction layer at the BOX/silicon interface that persists down to millikelvin temperatures. Standard-resistivity SOI performs better because dopant freeze-out suppresses bulk carrier loss, but it remains limited by residual substrate dissipation. Trap-rich SOI, with an engineered polycrystalline layer under the BOX, suppresses the parasitic sheet and reaches internal quality factors above 2×10^4 in the single-photon regime, with losses dominated by two-level s

Load-bearing premise

The assignment of HR SOI losses to parasitic sheet conduction rests on simulations that assume oxide charge densities of 10^10–10^12 cm^-2 at the BOX/silicon interface; the wafers' actual charge density is not measured, and if it fell below the ~10^10 cm^-2 threshold the proposed mechanism could not account for the factor-of-20 degradation relative to trap-rich SOI.

Editorial extensions

If this is right

  • Trap-rich SOI can serve as a low-loss substrate for superconducting circuits at millikelvin temperatures, with Qi above 2×10^4 at the single-photon level, already compatible with electromechanical and microwave-to-optical transducers.
  • For high-resistivity SOI, the buried-oxide interface acts as a loss channel: PSC losses limit Qi to about 10^3, so designers should avoid or neutralize this interface.
  • Because losses in trap-rich SOI are dominated by the SiO2 layer, changing the resonator geometry to reduce the oxide participation ratio offers a direct path to higher quality factors.
  • The temperature and power signatures of PSC losses—bell-shaped Qi and anomalous frequency shifts—differ from TLS losses, giving experimental fingerprints to identify PSC in other devices.
  • Keeping the buried oxide under static regions, rather than releasing it everywhere, preserves mechanical integrity and improves heat evacuation for nanomechanical devices.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same PSC mechanism likely degrades other cryogenic devices on insulator-on-semiconductor stacks (e.g., lithium niobate on insulator); a trap-rich layer could be a generic mitigation.
  • If the oxide charge density in standard SOI could be reduced below its ~10^11 cm^-2 threshold, standard-resistivity SOI might approach trap-rich performance without an extra processing layer.
  • The unexplained temperature-activated loss in trap-rich SOI above 250 mK, with no corresponding frequency shift, may originate in the polycrystalline trap layer itself; probing its 1/f permittivity noise could identify it and enable further improvement.
  • Measuring oxide charge density on the actual wafers would convert the simulation threshold from an assumption into a measured parameter, directly testing the PSC explanation.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper presents a comparative study of superconducting TiN microwave resonators fabricated on four substrates: high-resistivity bulk silicon, high-resistivity SOI, standard-resistivity SOI, and trap-rich SOI. At 25 mK the authors find that high-resistivity SOI performs worst (Qi ~10^3), standard SOI is intermediate, trap-rich SOI reaches Qi ~2–3×10^4 at the single-photon level, and HR bulk reaches ~2.5×10^5. They attribute the HR SOI degradation to a parasitic surface conduction (PSC) layer at the BOX/Si interface, the standard SOI limitation to residual bulk silicon dissipation, and the trap-rich SOI limitation to dielectric losses in the buried SiO2 layer. The support combines power and temperature dependence of Qi with 1D Poisson–Schrödinger simulations of PSC and electromagnetic simulations that map measured Qi to an effective PSC resistivity and then to an oxide charge density Qox.

Significance. If the mechanism attributions are correct, the work is significant for the integration of superconducting quantum circuits with SOI platforms: it overturns the default assumption that high-resistivity silicon is the best SOI choice, demonstrates a practical trap-rich alternative with Qi above 2×10^4, and identifies the BOX dielectric as the remaining loss channel. The empirical substrate ranking is well supported by the resonator measurements, and the paper includes several strengths: the same TiN process is used across all substrates, standard TLS and thermal-quasiparticle models are applied, the data are openly available, and the authors openly report where the TLS+QP model fails (trap-rich SOI above 250 mK). The main weakness is that the central mechanism attribution—particularly the PSC claim for HR SOI—rests on an inferred, not measured, oxide charge density Qox.

major comments (3)
  1. [§V.B, §V.C, Fig. 4d] The attribution of HR SOI losses to parasitic surface conduction depends on an unmeasured Qox. The simulations show a PSC threshold near 10^10 cm^-2 for HR SOI, and the measured Qi is matched by EM simulations using a 1-µm conducting layer, giving rho_eff ≈ 10 kΩ·cm and then mapping to Qox ≈ 10^10 cm^-2. For standard SOI the inferred Qox would be ≈10^11 cm^-2. However, no C-V, conductance, or Hall measurement on the actual wafers is reported (Section II only describes TiN van der Pauw characterization). If the real Qox on the HR SOI wafer were below ~10^10 cm^-2, the modeled PSC would be absent and the factor-of-20 degradation relative to trap-rich SOI would require another explanation. A direct measurement of Qox (or at least an upper bound) on the four wafers is needed to make the PSC attribution load-bearing rather than a consistency argument.
  2. [§V.A, §V.C, Fig. 3] The claim that trap-rich SOI is 'only limited by losses in the SiO2 layer' is not uniquely established. The Qi ≈ 23,000 value is estimated by electromagnetic simulation assuming tan δ_SiO2 ≈ 3×10^-4; no independent measurement of the BOX loss tangent or participation ratio is presented, and the same SiO2 BOX is not compared with a different thickness or geometry. Moreover, the temperature dependence in Fig. 3 shows an additional loss mechanism above 250 mK that the TLS+QP model fails to reproduce; the authors correctly flag this as unexplained and mention the poly-Si layer or top-Si resistivity as candidates. That unexplained channel could also contribute at base temperature. The text should either soften the exclusivity of the BOX-limited statement or provide additional experimental evidence (e.g., variable BOX thickness, or a direct loss-tangent measurement).
  3. [§IV, Eq. (4)] The thermal-QP model fit for the HR bulk substrate yields Δ0/h = 95 GHz, whereas the BCS estimate from Tc is Δ0/h = 132 GHz—about 28% lower. The text calls this 'comparable', but the discrepancy is large enough to indicate either a systematic issue in the QP model (e.g., the assumed kinetic inductance fraction or thin-film gap reduction) or a temperature calibration offset. Since this fitted Δ0 is then used as a fixed input for the trap-rich SOI analysis, the uncertainty in Δ0 propagates into the conclusion that thermal QPs are negligible in trap-rich SOI. A sensitivity check varying Δ0 within the uncertainty of the Tc measurement would strengthen that argument.
minor comments (6)
  1. [§II] Typo: 'chararectization' should be 'characterization'. Also 'buried oxied' in the second paragraph should be 'buried oxide'.
  2. [§I / Table I] The top-silicon layer resistivity is listed as ≈10 Ω·cm for all SOI substrates, but the paper does not state the top-silicon thickness for the standard SOI sample in the text (only in Table I). A brief sentence in Section II would help.
  3. [Fig. 2 and Table II] The fitting parameters for trap-rich SOI from the two datasets (Qc and Qc+) differ noticeably: Qi,sat = 19,000 vs 28,000 and β = 0.17 vs 0.27. The text notes the lower error bar for Qc+ but does not comment on whether the differences are statistically compatible. A short comment on the robustness of the TLS parameters would be useful.
  4. [§III, Eq. (3)] The notation '⟨n⟩' in Eq. (3) is not defined; it should be identified as ⟨n_photon⟩ from Eq. (2). Also, the normalization of the TLS saturation term with tanh(ℏω/2kBT) is standard but its derivation is not given; citing a recent review would help readers.
  5. [§IV, Fig. 3] The gray dashed exponential fits for standard SOI and HR SOI at high power are not described with fit parameters in the text or caption. State TX values (the text gives TX ≈ 300 mK for standard SOI only) and the fitting range.
  6. [§V.C] The sentence 'We do not expect such large variation of the defect density between the two substrates' is an assumption that should be explicitly flagged. Without Qox measurements this is a conjecture, not a conclusion.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the substrate ranking is empirical and the mechanistic attributions are consistency checks, not definitions.

full rationale

The paper's central result is an empirical ranking of four substrates measured with superconducting resonators: HR SOI is worst, Std SOI is intermediate, trap-rich SOI reaches Qi above 2e4, and HR bulk is best. This ranking is not derived from any assumed answer; it comes from fitting the measured S21 with a standard resonator model (Eq. 1) and extracting Qi. The TLS model (Eq. 3) is used to parameterize power and temperature dependencies, and the quasiparticle model (Eq. 4) is used to cross-check the HR bulk data; the paper explicitly reports that the QP model fails to capture the trap-rich SOI temperature dependence above 250 mK, and that the TLS model cannot fit Std SOI or HR SOI power dependence. These are honest non-circular checks. The PSC attribution for HR SOI is supported by 1D Poisson-Schrodinger simulations (Sec. V.B) that show a threshold at Qox ~1e10 cm^-2, and then by electromagnetic simulations that match the measured Qi using a 1-um conducting layer, yielding rho_eff ~10 kOhm.cm and a corresponding Qox near threshold. This is a model-based consistency argument, not a definitional reduction: Qox is not defined in terms of the measured Qi, and the paper does not claim to measure Qox on the actual wafers. The dependence on an unmeasured Qox is a legitimate scientific weakness, but it is a correctness/verification risk, not circularity. Self-citations (refs 19, 23, 24) provide film-growth and RF cryogenic context; they are not the sole evidence for the central claim, and the present data independently establish the substrate ranking and the failure of TLS and QP models on SOI substrates. No step in the derivation reduces by construction to its own inputs, so no circular step is identified.

Assumptions & free parameters 9 free parameters · 6 assumptions · 0 invented entities

The ledger is dominated by standard resonator-loss fitting parameters and literature-based substrate parameters rather than invented physics. The largest unmeasured inputs are Qox and per-wafer TiN consistency, both load-bearing for the PSC and BOX-limited conclusions.

free parameters (9)
  • Q_i,sat (trap-rich SOI) = 19,000 ± 4,000 (Qc=5300); 28,000 ± 1,000 (Qc=58000)
    Fit of Eq. 3 to power dependence; the single-photon limit depends on this value.
  • <n_c> = 48 ± 24; 37 ± 8
    Saturation photon number in TLS fit.
  • β = 0.17±0.04; 0.27±0.01; 0.81±0.03
    Empirical saturation exponent; used to infer the TLS bath character.
  • Q_i,other = >100,000; 190,000±30,000; 5.8×10^6±0.9×10^6
    Non-saturable loss term in Eq. 3 fit.
  • Δ0/h = 95 GHz
    Fit to HR bulk temperature data using TLS+QP model; then used to compute QP losses in trap-rich SOI.
  • T_X = ≈300 mK
    Empirical exp(-T/T_X) fit to standard-SOI high-power Qi data; origin unknown.
  • Q_ox (oxide charge density) = 10^10–10^12 cm^-2
    Chosen 'typical' values in PSC simulations, not measured on the actual wafers; determines whether PSC exists at 20 K.
  • ρ_eff (PSC sheet) = 33 kΩ·cm (Std); 10 kΩ·cm (HR)
    Inferred by matching EM-simulated Qi to measured Qi; then compared to Fig. 4d to estimate Q_ox.
  • tan δ_SiO2 = ≈3×10^-4
    Taken from literature to estimate that BOX loss yields Qi≈23,000, supporting the conclusion that trap-rich is BOX-limited.
assumptions (6)
  • domain assumption TLS saturation model (Eq. 3) with empirical β describes the saturable loss.
    Used to extract Qi,sat, nc, β, Qi,other for trap-rich and HR bulk; β=0.8 is expected for interface TLS but β≈0.3 for SOI is not fully explained.
  • domain assumption Thermal quasiparticle loss follows the thin-film Mattis–Bardeen expression (Eq. 4) with kinetic inductance fraction α.
    Used to separate QP losses from TLS in temperature fits.
  • domain assumption Positive charges in the buried oxide (Qox in 10^10–10^12 cm^-2) create an inversion layer at the BOX/Si interface that persists below dopant freeze-out when Qox exceeds a doping-dependent threshold.
    Basis for the PSC explanation; Qox is not measured on these wafers and the threshold is model-dependent.
  • domain assumption The TiN film and fabrication process are identical across the four substrate stacks, so Qi differences are substrate-induced.
    Only room-temperature TiN sheet resistance uniformity (<4%) is checked; per-wafer Tc is not reported.
  • domain assumption tan δ_SiO2 ≈ 3×10^-4, taken from prior literature, applies to the BOX layer in these wafers.
    Used to identify BOX dielectric loss as the limiting mechanism in trap-rich SOI.
  • standard math 1D Poisson–Schrödinger simulation with incomplete ionization and published mobility models adequately describes carrier freeze-out and inversion at 20 K.
    Supports the PSC threshold calculation shown in Fig. 4; relies on models from refs. 44–47.

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Cite this review

Pith. "Pith review of Origins of microwave losses in superconducting circuits made with silicon-on-insulator substrates." pith.science (2026). https://pith.science/paper/Z7OVL4DA

@misc{pith2026260729154,
  author       = {Pith},
  title        = {Pith review of: Origins of microwave losses in superconducting circuits made with silicon-on-insulator substrates},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/Z7OVL4DA}},
  note         = {Machine review of arXiv:2607.29154}
}
read the original abstract

Silicon-on-insulator technology is widely used to fabricate silicon based devices, from advanced transistors to photonic circuits or nanomechanical systems. Integrating low loss superconducting quantum circuits with silicon-on-insulator substrates enables to couple the advantages offered by the mature silicon technology to the exquisite sensitivity of superconducting circuits. The natural approach, inherited from research in superconducting microwave devices, is to use a substrate made with highly resistive silicon, known for its low level of microwave losses. In this work, using superconducting microwave resonators, we show that counterintuitively, standard resistivity silicon-on-insulator substrates perform better than high resistivity silicon-on-insulator substrates at cryogenic temperatures. In the latter case, the presence of a parasitic sheet conduction at the interface between bulk silicon and silicon oxide acts as the dominant loss mechanism. This parasitic sheet can be suppressed using substrates with intentionally induced traps. In such substrates, losses are ultimately limited by the dielectric losses of the silicon oxide layer. These substrates offer interesting perspectives for the development of superconducting nanoelectromechanical systems. First, the release, i.e. the removal of the silicon oxide, could be limited to the moving parts, thereby maintaining the mechanical integrity of the rest of the device. Additionally, such structure would enhance heat evacuation into the bulk of the substrate which is an issue in current devices such as microwave-to-optics converters.

Figures

Figures reproduced from arXiv: 2607.29154 by the authors.

Figure 1
Figure 1. Properties of the studied devices a) Schematic stacks of the studied devices for SOI trap-rich (left) and high-resistivity SOI or standard SOI (right) substrates. Carriers in square boxes denote trapped charges while carriers in circle are free carriers representing the parasitic surface conduction layer (PSC) that can exist in both high-resistivity (HR) and standard (STD) SOI substrates. This layer can have a signi… view at source ↗
Figure 2
Figure 2. Power dependence of internal quality factors Qi and resonance frequency shifts ∆fr. Data taken at 25 mK. a) Qi for the different substrates. Dashed lines are fits using a TLS based model described in the text for HR Bulk and trap-rich SOI substrates. Qc = 5300 and Qc+ = 58000 are the two different external quality factors used in this study. b) Shift of the resonance frequency with photon number: ∆fr = fr − fr,ref (… view at source ↗
Figure 3
Figure 3. Temperature dependence of internal quality factor and resonance frequency. Hollow marker data are taken at high microwave power (< nphoton >∼ 104 ), full marker data are taken at low microwave power (< nphoton >∼ 10−1 ). a) Qi for the different substrates. Colored dashed lines use a model of TLS (Eq. 3) and QP (Eq. 4) losses versus temperature at low power for HR bulk substrates (fitted parameters) and trap-rich SOI… view at source ↗
Figures from the paper (1 more)
Figure 4
Figure 4. Figure 4: Simulation of parasitic surface conduction layer (PSC) in p-doped SOI substrates. Calculation of the local charge density and resistivity in a structure composed of SiO2 (thickness tBOX=200 nm) and Si (thickness zmax=100 µm) (inset of b). Qox: positive charge defect de…

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Pith tools

Reviewed August 3, 2026 · model on record in the stance chip above.