Paper Citation Record · LEDGER

Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 6 inbound Pith citation observations for arXiv:1907.10701.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
1907.10701 v4

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 6 of 6 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00

measured 6 of 6 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-01T22:14:38.679513Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-25T02:20:14.417068Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation d3a05b38-cbbb-4da1-aef0-b2f90d4d2bd7 · inbound

Survival of the Cheapest: Cost-Aware Hardware Adaptation for Adversarial Robustness cites this paper.

Survival of the Cheapest: Cost-Aware Hardware Adaptation for Adversarial Robustness Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 32

Resolution: verified exact; arxiv_id, observed 2026-05-23T21:15:49.399879Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ae994997-f93c-458d-884c-7d7ba2c9ebb5 · inbound

Will LLMs Scaling Hit the Wall? Breaking Barriers via Distributed Resources on Massive Edge Devices cites this paper.

Will LLMs Scaling Hit the Wall? Breaking Barriers via Distributed Resources on Massive Edge Devices Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 134

Resolution: metadata mismatch; arxiv_id, observed 2026-05-23T01:05:16.335725Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 1d800c68-cbaa-46d4-a8d1-43f86d82617c · inbound

FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration cites this paper.

FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 29

Resolution: verified exact; arxiv_id, observed 2026-05-11T06:55:58.951271Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation f2e2a97c-6a0a-41fe-a829-bae645295e92 · inbound

Privatar: Scalable Privacy-preserving Multi-user VR via Secure Offloading cites this paper.

Privatar: Scalable Privacy-preserving Multi-user VR via Secure Offloading Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 79

Resolution: verified exact; arxiv_id, observed 2026-05-10T06:21:26.886374Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 5f51bbeb-b4f1-49e4-baa2-91e36b6643ea · inbound

DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration cites this paper.

DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 52

Resolution: verified exact; arxiv_id, observed 2026-05-25T02:20:14.420124Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 42033959-676d-4e5b-a287-59547366981c · inbound

DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction cites this paper.

DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 56

Resolution: unresolved; no resolver link, observed 2026-08-01T22:14:38.679513Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.